1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_ARMV7_PSCI_1_0 11 12 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 13 14 #define CONFIG_SYS_FSL_CLK 15 16 #define CONFIG_SKIP_LOWLEVEL_INIT 17 #define CONFIG_DEEP_SLEEP 18 19 /* 20 * Size of malloc() pool 21 */ 22 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 23 24 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 25 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 26 27 #define CONFIG_SYS_CLK_FREQ 100000000 28 #define CONFIG_DDR_CLK_FREQ 100000000 29 30 #define DDR_SDRAM_CFG 0x470c0008 31 #define DDR_CS0_BNDS 0x008000bf 32 #define DDR_CS0_CONFIG 0x80014302 33 #define DDR_TIMING_CFG_0 0x50550004 34 #define DDR_TIMING_CFG_1 0xbcb38c56 35 #define DDR_TIMING_CFG_2 0x0040d120 36 #define DDR_TIMING_CFG_3 0x010e1000 37 #define DDR_TIMING_CFG_4 0x00000001 38 #define DDR_TIMING_CFG_5 0x03401400 39 #define DDR_SDRAM_CFG_2 0x00401010 40 #define DDR_SDRAM_MODE 0x00061c60 41 #define DDR_SDRAM_MODE_2 0x00180000 42 #define DDR_SDRAM_INTERVAL 0x18600618 43 #define DDR_DDR_WRLVL_CNTL 0x8655f605 44 #define DDR_DDR_WRLVL_CNTL_2 0x05060607 45 #define DDR_DDR_WRLVL_CNTL_3 0x05050505 46 #define DDR_DDR_CDR1 0x80040000 47 #define DDR_DDR_CDR2 0x00000001 48 #define DDR_SDRAM_CLK_CNTL 0x02000000 49 #define DDR_DDR_ZQ_CNTL 0x89080600 50 #define DDR_CS0_CONFIG_2 0 51 #define DDR_SDRAM_CFG_MEM_EN 0x80000000 52 #define SDRAM_CFG2_D_INIT 0x00000010 53 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080 54 #define SDRAM_CFG2_FRC_SR 0x80000000 55 #define SDRAM_CFG_BI 0x00000001 56 57 #ifdef CONFIG_RAMBOOT_PBL 58 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg 59 #endif 60 61 #ifdef CONFIG_SD_BOOT 62 #ifdef CONFIG_SD_BOOT_QSPI 63 #define CONFIG_SYS_FSL_PBL_RCW \ 64 board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg 65 #else 66 #define CONFIG_SYS_FSL_PBL_RCW \ 67 board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg 68 #endif 69 #define CONFIG_SPL_FRAMEWORK 70 71 #ifdef CONFIG_SECURE_BOOT 72 /* 73 * HDR would be appended at end of image and copied to DDR along 74 * with U-Boot image. 75 */ 76 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 77 #endif /* ifdef CONFIG_SECURE_BOOT */ 78 79 #define CONFIG_SPL_TEXT_BASE 0x10000000 80 #define CONFIG_SPL_MAX_SIZE 0x1a000 81 #define CONFIG_SPL_STACK 0x1001d000 82 #define CONFIG_SPL_PAD_TO 0x1c000 83 #define CONFIG_SYS_TEXT_BASE 0x82000000 84 85 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 86 CONFIG_SYS_MONITOR_LEN) 87 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 88 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 89 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 90 91 #ifdef CONFIG_U_BOOT_HDR_SIZE 92 /* 93 * HDR would be appended at end of image and copied to DDR along 94 * with U-Boot image. Here u-boot max. size is 512K. So if binary 95 * size increases then increase this size in case of secure boot as 96 * it uses raw u-boot image instead of fit image. 97 */ 98 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) 99 #else 100 #define CONFIG_SYS_MONITOR_LEN 0x100000 101 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ 102 #endif 103 104 #ifdef CONFIG_QSPI_BOOT 105 #define CONFIG_SYS_TEXT_BASE 0x40100000 106 #endif 107 108 #ifndef CONFIG_SYS_TEXT_BASE 109 #define CONFIG_SYS_TEXT_BASE 0x60100000 110 #endif 111 112 #define CONFIG_NR_DRAM_BANKS 1 113 #define PHYS_SDRAM 0x80000000 114 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) 115 116 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 117 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 118 119 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ 120 !defined(CONFIG_QSPI_BOOT) 121 #define CONFIG_U_QE 122 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 123 #endif 124 125 /* 126 * IFC Definitions 127 */ 128 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 129 #define CONFIG_FSL_IFC 130 #define CONFIG_SYS_FLASH_BASE 0x60000000 131 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 132 133 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 134 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 135 CSPR_PORT_SIZE_16 | \ 136 CSPR_MSEL_NOR | \ 137 CSPR_V) 138 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 139 140 /* NOR Flash Timing Params */ 141 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 142 CSOR_NOR_TRHZ_80) 143 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 144 FTIM0_NOR_TEADC(0x5) | \ 145 FTIM0_NOR_TAVDS(0x0) | \ 146 FTIM0_NOR_TEAHC(0x5)) 147 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 148 FTIM1_NOR_TRAD_NOR(0x1A) | \ 149 FTIM1_NOR_TSEQRAD_NOR(0x13)) 150 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 151 FTIM2_NOR_TCH(0x4) | \ 152 FTIM2_NOR_TWP(0x1c) | \ 153 FTIM2_NOR_TWPH(0x0e)) 154 #define CONFIG_SYS_NOR_FTIM3 0 155 156 #define CONFIG_FLASH_CFI_DRIVER 157 #define CONFIG_SYS_FLASH_CFI 158 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 159 #define CONFIG_SYS_FLASH_QUIET_TEST 160 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 161 162 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 163 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 164 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 165 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 166 167 #define CONFIG_SYS_FLASH_EMPTY_INFO 168 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 169 170 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 171 #define CONFIG_SYS_WRITE_SWAPPED_DATA 172 #endif 173 174 /* CPLD */ 175 176 #define CONFIG_SYS_CPLD_BASE 0x7fb00000 177 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 178 179 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 180 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ 181 CSPR_PORT_SIZE_8 | \ 182 CSPR_MSEL_GPCM | \ 183 CSPR_V) 184 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 185 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 186 CSOR_NOR_NOR_MODE_AVD_NOR | \ 187 CSOR_NOR_TRHZ_80) 188 189 /* CPLD Timing parameters for IFC GPCM */ 190 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ 191 FTIM0_GPCM_TEADC(0xf) | \ 192 FTIM0_GPCM_TEAHC(0xf)) 193 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 194 FTIM1_GPCM_TRAD(0x3f)) 195 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 196 FTIM2_GPCM_TCH(0xf) | \ 197 FTIM2_GPCM_TWP(0xff)) 198 #define CONFIG_SYS_FPGA_FTIM3 0x0 199 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 200 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 201 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 202 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 203 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 204 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 205 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 206 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 207 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT 208 #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR 209 #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK 210 #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR 211 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0 212 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1 213 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2 214 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3 215 216 /* 217 * Serial Port 218 */ 219 #ifdef CONFIG_LPUART 220 #define CONFIG_LPUART_32B_REG 221 #else 222 #define CONFIG_CONS_INDEX 1 223 #define CONFIG_SYS_NS16550_SERIAL 224 #ifndef CONFIG_DM_SERIAL 225 #define CONFIG_SYS_NS16550_REG_SIZE 1 226 #endif 227 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 228 #endif 229 230 /* 231 * I2C 232 */ 233 #define CONFIG_SYS_I2C 234 #define CONFIG_SYS_I2C_MXC 235 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 236 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 237 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 238 239 /* EEPROM */ 240 #define CONFIG_ID_EEPROM 241 #define CONFIG_SYS_I2C_EEPROM_NXID 242 #define CONFIG_SYS_EEPROM_BUS_NUM 1 243 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 244 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 245 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 246 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 247 248 /* 249 * MMC 250 */ 251 #define CONFIG_FSL_ESDHC 252 253 /* SPI */ 254 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 255 /* QSPI */ 256 #define QSPI0_AMBA_BASE 0x40000000 257 #define FSL_QSPI_FLASH_SIZE (1 << 24) 258 #define FSL_QSPI_FLASH_NUM 2 259 260 /* DSPI */ 261 #endif 262 263 /* DM SPI */ 264 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 265 #define CONFIG_DM_SPI_FLASH 266 #endif 267 268 /* 269 * Video 270 */ 271 #ifdef CONFIG_VIDEO_FSL_DCU_FB 272 #define CONFIG_VIDEO_LOGO 273 #define CONFIG_VIDEO_BMP_LOGO 274 275 #define CONFIG_FSL_DCU_SII9022A 276 #define CONFIG_SYS_I2C_DVI_BUS_NUM 1 277 #define CONFIG_SYS_I2C_DVI_ADDR 0x39 278 #endif 279 280 /* 281 * eTSEC 282 */ 283 #define CONFIG_TSEC_ENET 284 285 #ifdef CONFIG_TSEC_ENET 286 #define CONFIG_MII 287 #define CONFIG_MII_DEFAULT_TSEC 1 288 #define CONFIG_TSEC1 1 289 #define CONFIG_TSEC1_NAME "eTSEC1" 290 #define CONFIG_TSEC2 1 291 #define CONFIG_TSEC2_NAME "eTSEC2" 292 #define CONFIG_TSEC3 1 293 #define CONFIG_TSEC3_NAME "eTSEC3" 294 295 #define TSEC1_PHY_ADDR 2 296 #define TSEC2_PHY_ADDR 0 297 #define TSEC3_PHY_ADDR 1 298 299 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 300 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 301 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 302 303 #define TSEC1_PHYIDX 0 304 #define TSEC2_PHYIDX 0 305 #define TSEC3_PHYIDX 0 306 307 #define CONFIG_ETHPRIME "eTSEC1" 308 309 #define CONFIG_PHY_ATHEROS 310 311 #define CONFIG_HAS_ETH0 312 #define CONFIG_HAS_ETH1 313 #define CONFIG_HAS_ETH2 314 #endif 315 316 /* PCIe */ 317 #define CONFIG_PCIE1 /* PCIE controller 1 */ 318 #define CONFIG_PCIE2 /* PCIE controller 2 */ 319 320 #ifdef CONFIG_PCI 321 #define CONFIG_PCI_SCAN_SHOW 322 #endif 323 324 #define CONFIG_CMDLINE_TAG 325 326 #define CONFIG_PEN_ADDR_BIG_ENDIAN 327 #define CONFIG_LAYERSCAPE_NS_ACCESS 328 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 329 #define COUNTER_FREQUENCY 12500000 330 331 #define CONFIG_HWCONFIG 332 #define HWCONFIG_BUFFER_SIZE 256 333 334 #define CONFIG_FSL_DEVICE_DISABLE 335 336 #include <config_distro_defaults.h> 337 #define BOOT_TARGET_DEVICES(func) \ 338 func(MMC, mmc, 0) \ 339 func(USB, usb, 0) 340 #include <config_distro_bootcmd.h> 341 342 #ifdef CONFIG_LPUART 343 #define CONFIG_EXTRA_ENV_SETTINGS \ 344 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ 345 "initrd_high=0xffffffff\0" \ 346 "fdt_high=0xffffffff\0" \ 347 "fdt_addr=0x64f00000\0" \ 348 "kernel_addr=0x65000000\0" \ 349 "scriptaddr=0x80000000\0" \ 350 "scripthdraddr=0x80080000\0" \ 351 "fdtheader_addr_r=0x80100000\0" \ 352 "kernelheader_addr_r=0x80200000\0" \ 353 "kernel_addr_r=0x81000000\0" \ 354 "fdt_addr_r=0x90000000\0" \ 355 "ramdisk_addr_r=0xa0000000\0" \ 356 "load_addr=0xa0000000\0" \ 357 "kernel_size=0x2800000\0" \ 358 "kernel_addr_sd=0x8000\0" \ 359 "kernel_size_sd=0x14000\0" \ 360 BOOTENV \ 361 "boot_scripts=ls1021atwr_boot.scr\0" \ 362 "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \ 363 "scan_dev_for_boot_part=" \ 364 "part list ${devtype} ${devnum} devplist; " \ 365 "env exists devplist || setenv devplist 1; " \ 366 "for distro_bootpart in ${devplist}; do " \ 367 "if fstype ${devtype} " \ 368 "${devnum}:${distro_bootpart} " \ 369 "bootfstype; then " \ 370 "run scan_dev_for_boot; " \ 371 "fi; " \ 372 "done\0" \ 373 "scan_dev_for_boot=" \ 374 "echo Scanning ${devtype} " \ 375 "${devnum}:${distro_bootpart}...; " \ 376 "for prefix in ${boot_prefixes}; do " \ 377 "run scan_dev_for_scripts; " \ 378 "done;" \ 379 "\0" \ 380 "boot_a_script=" \ 381 "load ${devtype} ${devnum}:${distro_bootpart} " \ 382 "${scriptaddr} ${prefix}${script}; " \ 383 "env exists secureboot && load ${devtype} " \ 384 "${devnum}:${distro_bootpart} " \ 385 "${scripthdraddr} ${prefix}${boot_script_hdr} " \ 386 "&& esbc_validate ${scripthdraddr};" \ 387 "source ${scriptaddr}\0" \ 388 "installer=load mmc 0:2 $load_addr " \ 389 "/flex_installer_arm32.itb; " \ 390 "bootm $load_addr#ls1021atwr\0" \ 391 "qspi_bootcmd=echo Trying load from qspi..;" \ 392 "sf probe && sf read $load_addr " \ 393 "$kernel_addr $kernel_size && bootm $load_addr#$board\0" \ 394 "nor_bootcmd=echo Trying load from nor..;" \ 395 "cp.b $kernel_addr $load_addr " \ 396 "$kernel_size && bootm $load_addr#$board\0" 397 #else 398 #define CONFIG_EXTRA_ENV_SETTINGS \ 399 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 400 "initrd_high=0xffffffff\0" \ 401 "fdt_high=0xffffffff\0" \ 402 "fdt_addr=0x64f00000\0" \ 403 "kernel_addr=0x61000000\0" \ 404 "kernelheader_addr=0x60800000\0" \ 405 "scriptaddr=0x80000000\0" \ 406 "scripthdraddr=0x80080000\0" \ 407 "fdtheader_addr_r=0x80100000\0" \ 408 "kernelheader_addr_r=0x80200000\0" \ 409 "kernel_addr_r=0x81000000\0" \ 410 "kernelheader_size=0x40000\0" \ 411 "fdt_addr_r=0x90000000\0" \ 412 "ramdisk_addr_r=0xa0000000\0" \ 413 "load_addr=0xa0000000\0" \ 414 "kernel_size=0x2800000\0" \ 415 "kernel_addr_sd=0x8000\0" \ 416 "kernel_size_sd=0x14000\0" \ 417 "kernelhdr_addr_sd=0x4000\0" \ 418 "kernelhdr_size_sd=0x10\0" \ 419 BOOTENV \ 420 "boot_scripts=ls1021atwr_boot.scr\0" \ 421 "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \ 422 "scan_dev_for_boot_part=" \ 423 "part list ${devtype} ${devnum} devplist; " \ 424 "env exists devplist || setenv devplist 1; " \ 425 "for distro_bootpart in ${devplist}; do " \ 426 "if fstype ${devtype} " \ 427 "${devnum}:${distro_bootpart} " \ 428 "bootfstype; then " \ 429 "run scan_dev_for_boot; " \ 430 "fi; " \ 431 "done\0" \ 432 "scan_dev_for_boot=" \ 433 "echo Scanning ${devtype} " \ 434 "${devnum}:${distro_bootpart}...; " \ 435 "for prefix in ${boot_prefixes}; do " \ 436 "run scan_dev_for_scripts; " \ 437 "done;" \ 438 "\0" \ 439 "boot_a_script=" \ 440 "load ${devtype} ${devnum}:${distro_bootpart} " \ 441 "${scriptaddr} ${prefix}${script}; " \ 442 "env exists secureboot && load ${devtype} " \ 443 "${devnum}:${distro_bootpart} " \ 444 "${scripthdraddr} ${prefix}${boot_script_hdr} " \ 445 "&& esbc_validate ${scripthdraddr};" \ 446 "source ${scriptaddr}\0" \ 447 "qspi_bootcmd=echo Trying load from qspi..;" \ 448 "sf probe && sf read $load_addr " \ 449 "$kernel_addr $kernel_size; env exists secureboot " \ 450 "&& sf read $kernelheader_addr_r $kernelheader_addr " \ 451 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ 452 "bootm $load_addr#$board\0" \ 453 "nor_bootcmd=echo Trying load from nor..;" \ 454 "cp.b $kernel_addr $load_addr " \ 455 "$kernel_size; env exists secureboot " \ 456 "&& cp.b $kernelheader_addr $kernelheader_addr_r " \ 457 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ 458 "bootm $load_addr#$board\0" \ 459 "sd_bootcmd=echo Trying load from SD ..;" \ 460 "mmcinfo && mmc read $load_addr " \ 461 "$kernel_addr_sd $kernel_size_sd && " \ 462 "env exists secureboot && mmc read $kernelheader_addr_r " \ 463 "$kernelhdr_addr_sd $kernelhdr_size_sd " \ 464 " && esbc_validate ${kernelheader_addr_r};" \ 465 "bootm $load_addr#$board\0" 466 #endif 467 468 #undef CONFIG_BOOTCOMMAND 469 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 470 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd" \ 471 "env exists secureboot && esbc_halt" 472 #elif defined(CONFIG_SD_BOOT) 473 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ 474 "env exists secureboot && esbc_halt;" 475 #else 476 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd;" \ 477 "env exists secureboot && esbc_halt;" 478 #endif 479 480 /* 481 * Miscellaneous configurable options 482 */ 483 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 484 #define CONFIG_AUTO_COMPLETE 485 486 #define CONFIG_SYS_MEMTEST_START 0x80000000 487 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 488 489 #define CONFIG_SYS_LOAD_ADDR 0x82000000 490 491 #define CONFIG_LS102XA_STREAM_ID 492 493 #define CONFIG_SYS_INIT_SP_OFFSET \ 494 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 495 #define CONFIG_SYS_INIT_SP_ADDR \ 496 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 497 498 #ifdef CONFIG_SPL_BUILD 499 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 500 #else 501 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 502 #endif 503 504 #define CONFIG_SYS_QE_FW_ADDR 0x60940000 505 506 /* 507 * Environment 508 */ 509 #define CONFIG_ENV_OVERWRITE 510 511 #if defined(CONFIG_SD_BOOT) 512 #define CONFIG_ENV_OFFSET 0x300000 513 #define CONFIG_SYS_MMC_ENV_DEV 0 514 #define CONFIG_ENV_SIZE 0x20000 515 #elif defined(CONFIG_QSPI_BOOT) 516 #define CONFIG_ENV_SIZE 0x2000 517 #define CONFIG_ENV_OFFSET 0x300000 518 #define CONFIG_ENV_SECT_SIZE 0x10000 519 #else 520 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 521 #define CONFIG_ENV_SIZE 0x20000 522 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 523 #endif 524 525 #define CONFIG_MISC_INIT_R 526 527 #include <asm/fsl_secure_boot.h> 528 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 529 530 #endif 531