1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_LS102XA 11 12 #define CONFIG_ARMV7_PSCI_1_0 13 14 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 15 16 #define CONFIG_SYS_FSL_CLK 17 18 #define CONFIG_SKIP_LOWLEVEL_INIT 19 #define CONFIG_BOARD_EARLY_INIT_F 20 #define CONFIG_DEEP_SLEEP 21 #ifdef CONFIG_DEEP_SLEEP 22 #define CONFIG_SILENT_CONSOLE 23 #endif 24 25 /* 26 * Size of malloc() pool 27 */ 28 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 29 30 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 31 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 32 33 /* 34 * USB 35 */ 36 37 /* 38 * EHCI Support - disbaled by default as 39 * there is no signal coming out of soc on 40 * this board for this controller. However, 41 * the silicon still has this controller, 42 * and anyone can use this controller by 43 * taking signals out on their board. 44 */ 45 46 /*#define CONFIG_HAS_FSL_DR_USB*/ 47 48 #ifdef CONFIG_HAS_FSL_DR_USB 49 #define CONFIG_USB_EHCI 50 #define CONFIG_USB_EHCI_FSL 51 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 52 #endif 53 54 /* XHCI Support - enabled by default */ 55 #define CONFIG_HAS_FSL_XHCI_USB 56 57 #ifdef CONFIG_HAS_FSL_XHCI_USB 58 #define CONFIG_USB_XHCI_FSL 59 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 60 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 61 #endif 62 63 /* 64 * Generic Timer Definitions 65 */ 66 #define GENERIC_TIMER_CLK 12500000 67 68 #define CONFIG_SYS_CLK_FREQ 100000000 69 #define CONFIG_DDR_CLK_FREQ 100000000 70 71 #define DDR_SDRAM_CFG 0x470c0008 72 #define DDR_CS0_BNDS 0x008000bf 73 #define DDR_CS0_CONFIG 0x80014302 74 #define DDR_TIMING_CFG_0 0x50550004 75 #define DDR_TIMING_CFG_1 0xbcb38c56 76 #define DDR_TIMING_CFG_2 0x0040d120 77 #define DDR_TIMING_CFG_3 0x010e1000 78 #define DDR_TIMING_CFG_4 0x00000001 79 #define DDR_TIMING_CFG_5 0x03401400 80 #define DDR_SDRAM_CFG_2 0x00401010 81 #define DDR_SDRAM_MODE 0x00061c60 82 #define DDR_SDRAM_MODE_2 0x00180000 83 #define DDR_SDRAM_INTERVAL 0x18600618 84 #define DDR_DDR_WRLVL_CNTL 0x8655f605 85 #define DDR_DDR_WRLVL_CNTL_2 0x05060607 86 #define DDR_DDR_WRLVL_CNTL_3 0x05050505 87 #define DDR_DDR_CDR1 0x80040000 88 #define DDR_DDR_CDR2 0x00000001 89 #define DDR_SDRAM_CLK_CNTL 0x02000000 90 #define DDR_DDR_ZQ_CNTL 0x89080600 91 #define DDR_CS0_CONFIG_2 0 92 #define DDR_SDRAM_CFG_MEM_EN 0x80000000 93 #define SDRAM_CFG2_D_INIT 0x00000010 94 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080 95 #define SDRAM_CFG2_FRC_SR 0x80000000 96 #define SDRAM_CFG_BI 0x00000001 97 98 #ifdef CONFIG_RAMBOOT_PBL 99 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg 100 #endif 101 102 #ifdef CONFIG_SD_BOOT 103 #ifdef CONFIG_SD_BOOT_QSPI 104 #define CONFIG_SYS_FSL_PBL_RCW \ 105 board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg 106 #else 107 #define CONFIG_SYS_FSL_PBL_RCW \ 108 board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg 109 #endif 110 #define CONFIG_SPL_FRAMEWORK 111 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 112 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 113 114 #ifdef CONFIG_SECURE_BOOT 115 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 116 /* 117 * HDR would be appended at end of image and copied to DDR along 118 * with U-Boot image. 119 */ 120 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS (0x400 + \ 121 (CONFIG_U_BOOT_HDR_SIZE / 512) 122 #else 123 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 124 #endif /* ifdef CONFIG_SECURE_BOOT */ 125 126 #define CONFIG_SPL_TEXT_BASE 0x10000000 127 #define CONFIG_SPL_MAX_SIZE 0x1a000 128 #define CONFIG_SPL_STACK 0x1001d000 129 #define CONFIG_SPL_PAD_TO 0x1c000 130 #define CONFIG_SYS_TEXT_BASE 0x82000000 131 132 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 133 CONFIG_SYS_MONITOR_LEN) 134 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 135 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 136 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 137 138 #ifdef CONFIG_U_BOOT_HDR_SIZE 139 /* 140 * HDR would be appended at end of image and copied to DDR along 141 * with U-Boot image. Here u-boot max. size is 512K. So if binary 142 * size increases then increase this size in case of secure boot as 143 * it uses raw u-boot image instead of fit image. 144 */ 145 #define CONFIG_SYS_MONITOR_LEN (0x80000 + CONFIG_U_BOOT_HDR_SIZE) 146 #else 147 #define CONFIG_SYS_MONITOR_LEN 0x80000 148 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ 149 #endif 150 151 #ifdef CONFIG_QSPI_BOOT 152 #define CONFIG_SYS_TEXT_BASE 0x40010000 153 #endif 154 155 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 156 #define CONFIG_SYS_NO_FLASH 157 #endif 158 159 #ifndef CONFIG_SYS_TEXT_BASE 160 #define CONFIG_SYS_TEXT_BASE 0x60100000 161 #endif 162 163 #define CONFIG_NR_DRAM_BANKS 1 164 #define PHYS_SDRAM 0x80000000 165 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) 166 167 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 168 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 169 170 #define CONFIG_FSL_CAAM /* Enable CAAM */ 171 172 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ 173 !defined(CONFIG_QSPI_BOOT) 174 #define CONFIG_U_QE 175 #endif 176 177 /* 178 * IFC Definitions 179 */ 180 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 181 #define CONFIG_FSL_IFC 182 #define CONFIG_SYS_FLASH_BASE 0x60000000 183 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 184 185 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 186 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 187 CSPR_PORT_SIZE_16 | \ 188 CSPR_MSEL_NOR | \ 189 CSPR_V) 190 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 191 192 /* NOR Flash Timing Params */ 193 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 194 CSOR_NOR_TRHZ_80) 195 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 196 FTIM0_NOR_TEADC(0x5) | \ 197 FTIM0_NOR_TAVDS(0x0) | \ 198 FTIM0_NOR_TEAHC(0x5)) 199 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 200 FTIM1_NOR_TRAD_NOR(0x1A) | \ 201 FTIM1_NOR_TSEQRAD_NOR(0x13)) 202 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 203 FTIM2_NOR_TCH(0x4) | \ 204 FTIM2_NOR_TWP(0x1c) | \ 205 FTIM2_NOR_TWPH(0x0e)) 206 #define CONFIG_SYS_NOR_FTIM3 0 207 208 #define CONFIG_FLASH_CFI_DRIVER 209 #define CONFIG_SYS_FLASH_CFI 210 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 211 #define CONFIG_SYS_FLASH_QUIET_TEST 212 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 213 214 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 215 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 216 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 217 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 218 219 #define CONFIG_SYS_FLASH_EMPTY_INFO 220 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 221 222 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 223 #define CONFIG_SYS_WRITE_SWAPPED_DATA 224 #endif 225 226 /* CPLD */ 227 228 #define CONFIG_SYS_CPLD_BASE 0x7fb00000 229 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 230 231 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 232 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ 233 CSPR_PORT_SIZE_8 | \ 234 CSPR_MSEL_GPCM | \ 235 CSPR_V) 236 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 237 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 238 CSOR_NOR_NOR_MODE_AVD_NOR | \ 239 CSOR_NOR_TRHZ_80) 240 241 /* CPLD Timing parameters for IFC GPCM */ 242 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ 243 FTIM0_GPCM_TEADC(0xf) | \ 244 FTIM0_GPCM_TEAHC(0xf)) 245 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 246 FTIM1_GPCM_TRAD(0x3f)) 247 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 248 FTIM2_GPCM_TCH(0xf) | \ 249 FTIM2_GPCM_TWP(0xff)) 250 #define CONFIG_SYS_FPGA_FTIM3 0x0 251 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 252 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 253 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 254 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 255 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 256 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 257 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 258 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 259 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT 260 #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR 261 #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK 262 #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR 263 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0 264 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1 265 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2 266 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3 267 268 /* 269 * Serial Port 270 */ 271 #ifdef CONFIG_LPUART 272 #define CONFIG_LPUART_32B_REG 273 #else 274 #define CONFIG_CONS_INDEX 1 275 #define CONFIG_SYS_NS16550_SERIAL 276 #ifndef CONFIG_DM_SERIAL 277 #define CONFIG_SYS_NS16550_REG_SIZE 1 278 #endif 279 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 280 #endif 281 282 #define CONFIG_BAUDRATE 115200 283 284 /* 285 * I2C 286 */ 287 #define CONFIG_SYS_I2C 288 #define CONFIG_SYS_I2C_MXC 289 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 290 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 291 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 292 293 /* EEPROM */ 294 #define CONFIG_ID_EEPROM 295 #define CONFIG_SYS_I2C_EEPROM_NXID 296 #define CONFIG_SYS_EEPROM_BUS_NUM 1 297 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 298 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 299 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 300 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 301 302 /* 303 * MMC 304 */ 305 #define CONFIG_MMC 306 #define CONFIG_FSL_ESDHC 307 #define CONFIG_GENERIC_MMC 308 309 #define CONFIG_DOS_PARTITION 310 311 /* SPI */ 312 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 313 /* QSPI */ 314 #define QSPI0_AMBA_BASE 0x40000000 315 #define FSL_QSPI_FLASH_SIZE (1 << 24) 316 #define FSL_QSPI_FLASH_NUM 2 317 318 /* DSPI */ 319 #endif 320 321 /* DM SPI */ 322 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 323 #define CONFIG_DM_SPI_FLASH 324 #endif 325 326 /* 327 * Video 328 */ 329 #define CONFIG_FSL_DCU_FB 330 331 #ifdef CONFIG_FSL_DCU_FB 332 #define CONFIG_VIDEO 333 #define CONFIG_CMD_BMP 334 #define CONFIG_CFB_CONSOLE 335 #define CONFIG_VGA_AS_SINGLE_DEVICE 336 #define CONFIG_VIDEO_LOGO 337 #define CONFIG_VIDEO_BMP_LOGO 338 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 339 340 #define CONFIG_FSL_DCU_SII9022A 341 #define CONFIG_SYS_I2C_DVI_BUS_NUM 1 342 #define CONFIG_SYS_I2C_DVI_ADDR 0x39 343 #endif 344 345 /* 346 * eTSEC 347 */ 348 #define CONFIG_TSEC_ENET 349 350 #ifdef CONFIG_TSEC_ENET 351 #define CONFIG_MII 352 #define CONFIG_MII_DEFAULT_TSEC 1 353 #define CONFIG_TSEC1 1 354 #define CONFIG_TSEC1_NAME "eTSEC1" 355 #define CONFIG_TSEC2 1 356 #define CONFIG_TSEC2_NAME "eTSEC2" 357 #define CONFIG_TSEC3 1 358 #define CONFIG_TSEC3_NAME "eTSEC3" 359 360 #define TSEC1_PHY_ADDR 2 361 #define TSEC2_PHY_ADDR 0 362 #define TSEC3_PHY_ADDR 1 363 364 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 365 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 366 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 367 368 #define TSEC1_PHYIDX 0 369 #define TSEC2_PHYIDX 0 370 #define TSEC3_PHYIDX 0 371 372 #define CONFIG_ETHPRIME "eTSEC1" 373 374 #define CONFIG_PHY_GIGE 375 #define CONFIG_PHYLIB 376 #define CONFIG_PHY_ATHEROS 377 378 #define CONFIG_HAS_ETH0 379 #define CONFIG_HAS_ETH1 380 #define CONFIG_HAS_ETH2 381 #endif 382 383 /* PCIe */ 384 #define CONFIG_PCI /* Enable PCI/PCIE */ 385 #define CONFIG_PCIE1 /* PCIE controller 1 */ 386 #define CONFIG_PCIE2 /* PCIE controller 2 */ 387 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 388 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" 389 390 #define CONFIG_SYS_PCI_64BIT 391 392 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 393 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ 394 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 395 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ 396 397 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 398 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 399 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ 400 401 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 402 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 403 #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ 404 405 #ifdef CONFIG_PCI 406 #define CONFIG_PCI_PNP 407 #define CONFIG_PCI_SCAN_SHOW 408 #define CONFIG_CMD_PCI 409 #endif 410 411 #define CONFIG_CMDLINE_TAG 412 #define CONFIG_CMDLINE_EDITING 413 414 #define CONFIG_PEN_ADDR_BIG_ENDIAN 415 #define CONFIG_LAYERSCAPE_NS_ACCESS 416 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 417 #define CONFIG_TIMER_CLK_FREQ 12500000 418 419 #define CONFIG_HWCONFIG 420 #define HWCONFIG_BUFFER_SIZE 256 421 422 #define CONFIG_FSL_DEVICE_DISABLE 423 424 425 #ifdef CONFIG_LPUART 426 #define CONFIG_EXTRA_ENV_SETTINGS \ 427 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ 428 "initrd_high=0xffffffff\0" \ 429 "fdt_high=0xffffffff\0" 430 #else 431 #define CONFIG_EXTRA_ENV_SETTINGS \ 432 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 433 "initrd_high=0xffffffff\0" \ 434 "fdt_high=0xffffffff\0" 435 #endif 436 437 /* 438 * Miscellaneous configurable options 439 */ 440 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 441 #define CONFIG_AUTO_COMPLETE 442 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 443 #define CONFIG_SYS_PBSIZE \ 444 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 445 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 446 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 447 448 #define CONFIG_SYS_MEMTEST_START 0x80000000 449 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 450 451 #define CONFIG_SYS_LOAD_ADDR 0x82000000 452 453 #define CONFIG_LS102XA_STREAM_ID 454 455 /* 456 * Stack sizes 457 * The stack sizes are set up in start.S using the settings below 458 */ 459 #define CONFIG_STACKSIZE (30 * 1024) 460 461 #define CONFIG_SYS_INIT_SP_OFFSET \ 462 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 463 #define CONFIG_SYS_INIT_SP_ADDR \ 464 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 465 466 #ifdef CONFIG_SPL_BUILD 467 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 468 #else 469 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 470 #endif 471 472 #define CONFIG_SYS_QE_FW_ADDR 0x600c0000 473 474 /* 475 * Environment 476 */ 477 #define CONFIG_ENV_OVERWRITE 478 479 #if defined(CONFIG_SD_BOOT) 480 #define CONFIG_ENV_OFFSET 0x100000 481 #define CONFIG_ENV_IS_IN_MMC 482 #define CONFIG_SYS_MMC_ENV_DEV 0 483 #define CONFIG_ENV_SIZE 0x20000 484 #elif defined(CONFIG_QSPI_BOOT) 485 #define CONFIG_ENV_IS_IN_SPI_FLASH 486 #define CONFIG_ENV_SIZE 0x2000 487 #define CONFIG_ENV_OFFSET 0x100000 488 #define CONFIG_ENV_SECT_SIZE 0x10000 489 #else 490 #define CONFIG_ENV_IS_IN_FLASH 491 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 492 #define CONFIG_ENV_SIZE 0x20000 493 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 494 #endif 495 496 #define CONFIG_MISC_INIT_R 497 498 /* Hash command with SHA acceleration supported in hardware */ 499 #ifdef CONFIG_FSL_CAAM 500 #define CONFIG_CMD_HASH 501 #define CONFIG_SHA_HW_ACCEL 502 #endif 503 504 #include <asm/fsl_secure_boot.h> 505 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 506 507 #endif 508