1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __CONFIG_H 7 #define __CONFIG_H 8 9 #define CONFIG_ARMV7_PSCI_1_0 10 11 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 12 13 #define CONFIG_SYS_FSL_CLK 14 15 #define CONFIG_SKIP_LOWLEVEL_INIT 16 #define CONFIG_DEEP_SLEEP 17 18 /* 19 * Size of malloc() pool 20 */ 21 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 22 23 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 24 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 25 26 #define CONFIG_SYS_CLK_FREQ 100000000 27 #define CONFIG_DDR_CLK_FREQ 100000000 28 29 #define DDR_SDRAM_CFG 0x470c0008 30 #define DDR_CS0_BNDS 0x008000bf 31 #define DDR_CS0_CONFIG 0x80014302 32 #define DDR_TIMING_CFG_0 0x50550004 33 #define DDR_TIMING_CFG_1 0xbcb38c56 34 #define DDR_TIMING_CFG_2 0x0040d120 35 #define DDR_TIMING_CFG_3 0x010e1000 36 #define DDR_TIMING_CFG_4 0x00000001 37 #define DDR_TIMING_CFG_5 0x03401400 38 #define DDR_SDRAM_CFG_2 0x00401010 39 #define DDR_SDRAM_MODE 0x00061c60 40 #define DDR_SDRAM_MODE_2 0x00180000 41 #define DDR_SDRAM_INTERVAL 0x18600618 42 #define DDR_DDR_WRLVL_CNTL 0x8655f605 43 #define DDR_DDR_WRLVL_CNTL_2 0x05060607 44 #define DDR_DDR_WRLVL_CNTL_3 0x05050505 45 #define DDR_DDR_CDR1 0x80040000 46 #define DDR_DDR_CDR2 0x00000001 47 #define DDR_SDRAM_CLK_CNTL 0x02000000 48 #define DDR_DDR_ZQ_CNTL 0x89080600 49 #define DDR_CS0_CONFIG_2 0 50 #define DDR_SDRAM_CFG_MEM_EN 0x80000000 51 #define SDRAM_CFG2_D_INIT 0x00000010 52 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080 53 #define SDRAM_CFG2_FRC_SR 0x80000000 54 #define SDRAM_CFG_BI 0x00000001 55 56 #ifdef CONFIG_RAMBOOT_PBL 57 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg 58 #endif 59 60 #ifdef CONFIG_SD_BOOT 61 #ifdef CONFIG_SD_BOOT_QSPI 62 #define CONFIG_SYS_FSL_PBL_RCW \ 63 board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg 64 #else 65 #define CONFIG_SYS_FSL_PBL_RCW \ 66 board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg 67 #endif 68 69 #ifdef CONFIG_SECURE_BOOT 70 /* 71 * HDR would be appended at end of image and copied to DDR along 72 * with U-Boot image. 73 */ 74 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 75 #endif /* ifdef CONFIG_SECURE_BOOT */ 76 77 #define CONFIG_SPL_TEXT_BASE 0x10000000 78 #define CONFIG_SPL_MAX_SIZE 0x1a000 79 #define CONFIG_SPL_STACK 0x1001d000 80 #define CONFIG_SPL_PAD_TO 0x1c000 81 82 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 83 CONFIG_SYS_MONITOR_LEN) 84 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 85 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 86 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 87 88 #ifdef CONFIG_U_BOOT_HDR_SIZE 89 /* 90 * HDR would be appended at end of image and copied to DDR along 91 * with U-Boot image. Here u-boot max. size is 512K. So if binary 92 * size increases then increase this size in case of secure boot as 93 * it uses raw u-boot image instead of fit image. 94 */ 95 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) 96 #else 97 #define CONFIG_SYS_MONITOR_LEN 0x100000 98 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ 99 #endif 100 101 #define PHYS_SDRAM 0x80000000 102 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) 103 104 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 105 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 106 107 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ 108 !defined(CONFIG_QSPI_BOOT) 109 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 110 #endif 111 112 /* 113 * IFC Definitions 114 */ 115 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 116 #define CONFIG_FSL_IFC 117 #define CONFIG_SYS_FLASH_BASE 0x60000000 118 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 119 120 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 121 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 122 CSPR_PORT_SIZE_16 | \ 123 CSPR_MSEL_NOR | \ 124 CSPR_V) 125 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 126 127 /* NOR Flash Timing Params */ 128 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 129 CSOR_NOR_TRHZ_80) 130 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 131 FTIM0_NOR_TEADC(0x5) | \ 132 FTIM0_NOR_TAVDS(0x0) | \ 133 FTIM0_NOR_TEAHC(0x5)) 134 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 135 FTIM1_NOR_TRAD_NOR(0x1A) | \ 136 FTIM1_NOR_TSEQRAD_NOR(0x13)) 137 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 138 FTIM2_NOR_TCH(0x4) | \ 139 FTIM2_NOR_TWP(0x1c) | \ 140 FTIM2_NOR_TWPH(0x0e)) 141 #define CONFIG_SYS_NOR_FTIM3 0 142 143 #define CONFIG_SYS_FLASH_QUIET_TEST 144 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 145 146 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 147 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 148 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 149 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 150 151 #define CONFIG_SYS_FLASH_EMPTY_INFO 152 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 153 154 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 155 #define CONFIG_SYS_WRITE_SWAPPED_DATA 156 #endif 157 158 /* CPLD */ 159 160 #define CONFIG_SYS_CPLD_BASE 0x7fb00000 161 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 162 163 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 164 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ 165 CSPR_PORT_SIZE_8 | \ 166 CSPR_MSEL_GPCM | \ 167 CSPR_V) 168 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 169 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 170 CSOR_NOR_NOR_MODE_AVD_NOR | \ 171 CSOR_NOR_TRHZ_80) 172 173 /* CPLD Timing parameters for IFC GPCM */ 174 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ 175 FTIM0_GPCM_TEADC(0xf) | \ 176 FTIM0_GPCM_TEAHC(0xf)) 177 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 178 FTIM1_GPCM_TRAD(0x3f)) 179 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 180 FTIM2_GPCM_TCH(0xf) | \ 181 FTIM2_GPCM_TWP(0xff)) 182 #define CONFIG_SYS_FPGA_FTIM3 0x0 183 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 184 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 185 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 186 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 187 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 188 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 189 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 190 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 191 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT 192 #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR 193 #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK 194 #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR 195 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0 196 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1 197 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2 198 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3 199 200 /* 201 * Serial Port 202 */ 203 #ifdef CONFIG_LPUART 204 #define CONFIG_LPUART_32B_REG 205 #else 206 #define CONFIG_SYS_NS16550_SERIAL 207 #ifndef CONFIG_DM_SERIAL 208 #define CONFIG_SYS_NS16550_REG_SIZE 1 209 #endif 210 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 211 #endif 212 213 /* 214 * I2C 215 */ 216 #define CONFIG_SYS_I2C 217 #define CONFIG_SYS_I2C_MXC 218 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 219 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 220 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 221 222 /* EEPROM */ 223 #define CONFIG_ID_EEPROM 224 #define CONFIG_SYS_I2C_EEPROM_NXID 225 #define CONFIG_SYS_EEPROM_BUS_NUM 1 226 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 227 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 228 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 229 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 230 231 /* 232 * MMC 233 */ 234 235 /* SPI */ 236 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 237 /* QSPI */ 238 #define QSPI0_AMBA_BASE 0x40000000 239 #define FSL_QSPI_FLASH_SIZE (1 << 24) 240 #define FSL_QSPI_FLASH_NUM 2 241 242 /* DSPI */ 243 #endif 244 245 /* DM SPI */ 246 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 247 #define CONFIG_DM_SPI_FLASH 248 #endif 249 250 /* 251 * Video 252 */ 253 #ifdef CONFIG_VIDEO_FSL_DCU_FB 254 #define CONFIG_VIDEO_LOGO 255 #define CONFIG_VIDEO_BMP_LOGO 256 257 #define CONFIG_FSL_DCU_SII9022A 258 #define CONFIG_SYS_I2C_DVI_BUS_NUM 1 259 #define CONFIG_SYS_I2C_DVI_ADDR 0x39 260 #endif 261 262 /* 263 * eTSEC 264 */ 265 266 #ifdef CONFIG_TSEC_ENET 267 #define CONFIG_MII_DEFAULT_TSEC 1 268 #define CONFIG_TSEC1 1 269 #define CONFIG_TSEC1_NAME "eTSEC1" 270 #define CONFIG_TSEC2 1 271 #define CONFIG_TSEC2_NAME "eTSEC2" 272 #define CONFIG_TSEC3 1 273 #define CONFIG_TSEC3_NAME "eTSEC3" 274 275 #define TSEC1_PHY_ADDR 2 276 #define TSEC2_PHY_ADDR 0 277 #define TSEC3_PHY_ADDR 1 278 279 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 280 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 281 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 282 283 #define TSEC1_PHYIDX 0 284 #define TSEC2_PHYIDX 0 285 #define TSEC3_PHYIDX 0 286 287 #define CONFIG_ETHPRIME "eTSEC1" 288 289 #define CONFIG_PHY_ATHEROS 290 291 #define CONFIG_HAS_ETH0 292 #define CONFIG_HAS_ETH1 293 #define CONFIG_HAS_ETH2 294 #endif 295 296 /* PCIe */ 297 #define CONFIG_PCIE1 /* PCIE controller 1 */ 298 #define CONFIG_PCIE2 /* PCIE controller 2 */ 299 300 #ifdef CONFIG_PCI 301 #define CONFIG_PCI_SCAN_SHOW 302 #endif 303 304 #define CONFIG_CMDLINE_TAG 305 306 #define CONFIG_PEN_ADDR_BIG_ENDIAN 307 #define CONFIG_LAYERSCAPE_NS_ACCESS 308 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 309 #define COUNTER_FREQUENCY 12500000 310 311 #define CONFIG_HWCONFIG 312 #define HWCONFIG_BUFFER_SIZE 256 313 314 #define CONFIG_FSL_DEVICE_DISABLE 315 316 #define BOOT_TARGET_DEVICES(func) \ 317 func(MMC, mmc, 0) \ 318 func(USB, usb, 0) 319 #include <config_distro_bootcmd.h> 320 321 #ifdef CONFIG_LPUART 322 #define CONFIG_EXTRA_ENV_SETTINGS \ 323 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ 324 "initrd_high=0xffffffff\0" \ 325 "fdt_high=0xffffffff\0" \ 326 "fdt_addr=0x64f00000\0" \ 327 "kernel_addr=0x65000000\0" \ 328 "scriptaddr=0x80000000\0" \ 329 "scripthdraddr=0x80080000\0" \ 330 "fdtheader_addr_r=0x80100000\0" \ 331 "kernelheader_addr_r=0x80200000\0" \ 332 "kernel_addr_r=0x81000000\0" \ 333 "fdt_addr_r=0x90000000\0" \ 334 "ramdisk_addr_r=0xa0000000\0" \ 335 "load_addr=0xa0000000\0" \ 336 "kernel_size=0x2800000\0" \ 337 "kernel_addr_sd=0x8000\0" \ 338 "kernel_size_sd=0x14000\0" \ 339 BOOTENV \ 340 "boot_scripts=ls1021atwr_boot.scr\0" \ 341 "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \ 342 "scan_dev_for_boot_part=" \ 343 "part list ${devtype} ${devnum} devplist; " \ 344 "env exists devplist || setenv devplist 1; " \ 345 "for distro_bootpart in ${devplist}; do " \ 346 "if fstype ${devtype} " \ 347 "${devnum}:${distro_bootpart} " \ 348 "bootfstype; then " \ 349 "run scan_dev_for_boot; " \ 350 "fi; " \ 351 "done\0" \ 352 "scan_dev_for_boot=" \ 353 "echo Scanning ${devtype} " \ 354 "${devnum}:${distro_bootpart}...; " \ 355 "for prefix in ${boot_prefixes}; do " \ 356 "run scan_dev_for_scripts; " \ 357 "done;" \ 358 "\0" \ 359 "boot_a_script=" \ 360 "load ${devtype} ${devnum}:${distro_bootpart} " \ 361 "${scriptaddr} ${prefix}${script}; " \ 362 "env exists secureboot && load ${devtype} " \ 363 "${devnum}:${distro_bootpart} " \ 364 "${scripthdraddr} ${prefix}${boot_script_hdr} " \ 365 "&& esbc_validate ${scripthdraddr};" \ 366 "source ${scriptaddr}\0" \ 367 "installer=load mmc 0:2 $load_addr " \ 368 "/flex_installer_arm32.itb; " \ 369 "bootm $load_addr#ls1021atwr\0" \ 370 "qspi_bootcmd=echo Trying load from qspi..;" \ 371 "sf probe && sf read $load_addr " \ 372 "$kernel_addr $kernel_size && bootm $load_addr#$board\0" \ 373 "nor_bootcmd=echo Trying load from nor..;" \ 374 "cp.b $kernel_addr $load_addr " \ 375 "$kernel_size && bootm $load_addr#$board\0" 376 #else 377 #define CONFIG_EXTRA_ENV_SETTINGS \ 378 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 379 "initrd_high=0xffffffff\0" \ 380 "fdt_high=0xffffffff\0" \ 381 "fdt_addr=0x64f00000\0" \ 382 "kernel_addr=0x61000000\0" \ 383 "kernelheader_addr=0x60800000\0" \ 384 "scriptaddr=0x80000000\0" \ 385 "scripthdraddr=0x80080000\0" \ 386 "fdtheader_addr_r=0x80100000\0" \ 387 "kernelheader_addr_r=0x80200000\0" \ 388 "kernel_addr_r=0x81000000\0" \ 389 "kernelheader_size=0x40000\0" \ 390 "fdt_addr_r=0x90000000\0" \ 391 "ramdisk_addr_r=0xa0000000\0" \ 392 "load_addr=0xa0000000\0" \ 393 "kernel_size=0x2800000\0" \ 394 "kernel_addr_sd=0x8000\0" \ 395 "kernel_size_sd=0x14000\0" \ 396 "kernelhdr_addr_sd=0x4000\0" \ 397 "kernelhdr_size_sd=0x10\0" \ 398 BOOTENV \ 399 "boot_scripts=ls1021atwr_boot.scr\0" \ 400 "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \ 401 "scan_dev_for_boot_part=" \ 402 "part list ${devtype} ${devnum} devplist; " \ 403 "env exists devplist || setenv devplist 1; " \ 404 "for distro_bootpart in ${devplist}; do " \ 405 "if fstype ${devtype} " \ 406 "${devnum}:${distro_bootpart} " \ 407 "bootfstype; then " \ 408 "run scan_dev_for_boot; " \ 409 "fi; " \ 410 "done\0" \ 411 "scan_dev_for_boot=" \ 412 "echo Scanning ${devtype} " \ 413 "${devnum}:${distro_bootpart}...; " \ 414 "for prefix in ${boot_prefixes}; do " \ 415 "run scan_dev_for_scripts; " \ 416 "done;" \ 417 "\0" \ 418 "boot_a_script=" \ 419 "load ${devtype} ${devnum}:${distro_bootpart} " \ 420 "${scriptaddr} ${prefix}${script}; " \ 421 "env exists secureboot && load ${devtype} " \ 422 "${devnum}:${distro_bootpart} " \ 423 "${scripthdraddr} ${prefix}${boot_script_hdr} " \ 424 "&& esbc_validate ${scripthdraddr};" \ 425 "source ${scriptaddr}\0" \ 426 "qspi_bootcmd=echo Trying load from qspi..;" \ 427 "sf probe && sf read $load_addr " \ 428 "$kernel_addr $kernel_size; env exists secureboot " \ 429 "&& sf read $kernelheader_addr_r $kernelheader_addr " \ 430 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ 431 "bootm $load_addr#$board\0" \ 432 "nor_bootcmd=echo Trying load from nor..;" \ 433 "cp.b $kernel_addr $load_addr " \ 434 "$kernel_size; env exists secureboot " \ 435 "&& cp.b $kernelheader_addr $kernelheader_addr_r " \ 436 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ 437 "bootm $load_addr#$board\0" \ 438 "sd_bootcmd=echo Trying load from SD ..;" \ 439 "mmcinfo && mmc read $load_addr " \ 440 "$kernel_addr_sd $kernel_size_sd && " \ 441 "env exists secureboot && mmc read $kernelheader_addr_r " \ 442 "$kernelhdr_addr_sd $kernelhdr_size_sd " \ 443 " && esbc_validate ${kernelheader_addr_r};" \ 444 "bootm $load_addr#$board\0" 445 #endif 446 447 #undef CONFIG_BOOTCOMMAND 448 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 449 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd" \ 450 "env exists secureboot && esbc_halt" 451 #elif defined(CONFIG_SD_BOOT) 452 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ 453 "env exists secureboot && esbc_halt;" 454 #else 455 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd;" \ 456 "env exists secureboot && esbc_halt;" 457 #endif 458 459 /* 460 * Miscellaneous configurable options 461 */ 462 463 #define CONFIG_SYS_MEMTEST_START 0x80000000 464 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 465 466 #define CONFIG_SYS_LOAD_ADDR 0x82000000 467 468 #define CONFIG_LS102XA_STREAM_ID 469 470 #define CONFIG_SYS_INIT_SP_OFFSET \ 471 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 472 #define CONFIG_SYS_INIT_SP_ADDR \ 473 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 474 475 #ifdef CONFIG_SPL_BUILD 476 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 477 #else 478 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 479 #endif 480 481 #define CONFIG_SYS_QE_FW_ADDR 0x60940000 482 483 /* 484 * Environment 485 */ 486 #define CONFIG_ENV_OVERWRITE 487 488 #if defined(CONFIG_SD_BOOT) 489 #define CONFIG_ENV_OFFSET 0x300000 490 #define CONFIG_SYS_MMC_ENV_DEV 0 491 #define CONFIG_ENV_SIZE 0x20000 492 #elif defined(CONFIG_QSPI_BOOT) 493 #define CONFIG_ENV_SIZE 0x2000 494 #define CONFIG_ENV_OFFSET 0x300000 495 #define CONFIG_ENV_SECT_SIZE 0x10000 496 #else 497 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 498 #define CONFIG_ENV_SIZE 0x20000 499 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 500 #endif 501 502 #include <asm/fsl_secure_boot.h> 503 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 504 505 #endif 506