1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_LS102XA 11 12 #define CONFIG_ARMV7_PSCI_1_0 13 14 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 15 16 #define CONFIG_SYS_FSL_CLK 17 18 #define CONFIG_SKIP_LOWLEVEL_INIT 19 #define CONFIG_DEEP_SLEEP 20 21 /* 22 * Size of malloc() pool 23 */ 24 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 25 26 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 27 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 28 29 /* 30 * USB 31 */ 32 33 /* 34 * EHCI Support - disbaled by default as 35 * there is no signal coming out of soc on 36 * this board for this controller. However, 37 * the silicon still has this controller, 38 * and anyone can use this controller by 39 * taking signals out on their board. 40 */ 41 42 /*#define CONFIG_HAS_FSL_DR_USB*/ 43 44 #ifdef CONFIG_HAS_FSL_DR_USB 45 #define CONFIG_USB_EHCI 46 #define CONFIG_USB_EHCI_FSL 47 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 48 #endif 49 50 /* XHCI Support - enabled by default */ 51 #define CONFIG_HAS_FSL_XHCI_USB 52 53 #ifdef CONFIG_HAS_FSL_XHCI_USB 54 #define CONFIG_USB_XHCI_FSL 55 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 56 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 57 #endif 58 59 /* 60 * Generic Timer Definitions 61 */ 62 #define GENERIC_TIMER_CLK 12500000 63 64 #define CONFIG_SYS_CLK_FREQ 100000000 65 #define CONFIG_DDR_CLK_FREQ 100000000 66 67 #define DDR_SDRAM_CFG 0x470c0008 68 #define DDR_CS0_BNDS 0x008000bf 69 #define DDR_CS0_CONFIG 0x80014302 70 #define DDR_TIMING_CFG_0 0x50550004 71 #define DDR_TIMING_CFG_1 0xbcb38c56 72 #define DDR_TIMING_CFG_2 0x0040d120 73 #define DDR_TIMING_CFG_3 0x010e1000 74 #define DDR_TIMING_CFG_4 0x00000001 75 #define DDR_TIMING_CFG_5 0x03401400 76 #define DDR_SDRAM_CFG_2 0x00401010 77 #define DDR_SDRAM_MODE 0x00061c60 78 #define DDR_SDRAM_MODE_2 0x00180000 79 #define DDR_SDRAM_INTERVAL 0x18600618 80 #define DDR_DDR_WRLVL_CNTL 0x8655f605 81 #define DDR_DDR_WRLVL_CNTL_2 0x05060607 82 #define DDR_DDR_WRLVL_CNTL_3 0x05050505 83 #define DDR_DDR_CDR1 0x80040000 84 #define DDR_DDR_CDR2 0x00000001 85 #define DDR_SDRAM_CLK_CNTL 0x02000000 86 #define DDR_DDR_ZQ_CNTL 0x89080600 87 #define DDR_CS0_CONFIG_2 0 88 #define DDR_SDRAM_CFG_MEM_EN 0x80000000 89 #define SDRAM_CFG2_D_INIT 0x00000010 90 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080 91 #define SDRAM_CFG2_FRC_SR 0x80000000 92 #define SDRAM_CFG_BI 0x00000001 93 94 #ifdef CONFIG_RAMBOOT_PBL 95 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg 96 #endif 97 98 #ifdef CONFIG_SD_BOOT 99 #ifdef CONFIG_SD_BOOT_QSPI 100 #define CONFIG_SYS_FSL_PBL_RCW \ 101 board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg 102 #else 103 #define CONFIG_SYS_FSL_PBL_RCW \ 104 board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg 105 #endif 106 #define CONFIG_SPL_FRAMEWORK 107 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 108 109 #ifdef CONFIG_SECURE_BOOT 110 /* 111 * HDR would be appended at end of image and copied to DDR along 112 * with U-Boot image. 113 */ 114 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 115 #endif /* ifdef CONFIG_SECURE_BOOT */ 116 117 #define CONFIG_SPL_TEXT_BASE 0x10000000 118 #define CONFIG_SPL_MAX_SIZE 0x1a000 119 #define CONFIG_SPL_STACK 0x1001d000 120 #define CONFIG_SPL_PAD_TO 0x1c000 121 #define CONFIG_SYS_TEXT_BASE 0x82000000 122 123 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 124 CONFIG_SYS_MONITOR_LEN) 125 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 126 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 127 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 128 129 #ifdef CONFIG_U_BOOT_HDR_SIZE 130 /* 131 * HDR would be appended at end of image and copied to DDR along 132 * with U-Boot image. Here u-boot max. size is 512K. So if binary 133 * size increases then increase this size in case of secure boot as 134 * it uses raw u-boot image instead of fit image. 135 */ 136 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) 137 #else 138 #define CONFIG_SYS_MONITOR_LEN 0x100000 139 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ 140 #endif 141 142 #ifdef CONFIG_QSPI_BOOT 143 #define CONFIG_SYS_TEXT_BASE 0x40010000 144 #endif 145 146 #ifndef CONFIG_SYS_TEXT_BASE 147 #define CONFIG_SYS_TEXT_BASE 0x60100000 148 #endif 149 150 #define CONFIG_NR_DRAM_BANKS 1 151 #define PHYS_SDRAM 0x80000000 152 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) 153 154 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 155 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 156 157 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ 158 !defined(CONFIG_QSPI_BOOT) 159 #define CONFIG_U_QE 160 #endif 161 162 /* 163 * IFC Definitions 164 */ 165 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 166 #define CONFIG_FSL_IFC 167 #define CONFIG_SYS_FLASH_BASE 0x60000000 168 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 169 170 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 171 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 172 CSPR_PORT_SIZE_16 | \ 173 CSPR_MSEL_NOR | \ 174 CSPR_V) 175 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 176 177 /* NOR Flash Timing Params */ 178 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 179 CSOR_NOR_TRHZ_80) 180 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 181 FTIM0_NOR_TEADC(0x5) | \ 182 FTIM0_NOR_TAVDS(0x0) | \ 183 FTIM0_NOR_TEAHC(0x5)) 184 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 185 FTIM1_NOR_TRAD_NOR(0x1A) | \ 186 FTIM1_NOR_TSEQRAD_NOR(0x13)) 187 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 188 FTIM2_NOR_TCH(0x4) | \ 189 FTIM2_NOR_TWP(0x1c) | \ 190 FTIM2_NOR_TWPH(0x0e)) 191 #define CONFIG_SYS_NOR_FTIM3 0 192 193 #define CONFIG_FLASH_CFI_DRIVER 194 #define CONFIG_SYS_FLASH_CFI 195 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 196 #define CONFIG_SYS_FLASH_QUIET_TEST 197 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 198 199 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 200 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 201 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 202 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 203 204 #define CONFIG_SYS_FLASH_EMPTY_INFO 205 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 206 207 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 208 #define CONFIG_SYS_WRITE_SWAPPED_DATA 209 #endif 210 211 /* CPLD */ 212 213 #define CONFIG_SYS_CPLD_BASE 0x7fb00000 214 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 215 216 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 217 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ 218 CSPR_PORT_SIZE_8 | \ 219 CSPR_MSEL_GPCM | \ 220 CSPR_V) 221 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 222 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 223 CSOR_NOR_NOR_MODE_AVD_NOR | \ 224 CSOR_NOR_TRHZ_80) 225 226 /* CPLD Timing parameters for IFC GPCM */ 227 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ 228 FTIM0_GPCM_TEADC(0xf) | \ 229 FTIM0_GPCM_TEAHC(0xf)) 230 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 231 FTIM1_GPCM_TRAD(0x3f)) 232 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 233 FTIM2_GPCM_TCH(0xf) | \ 234 FTIM2_GPCM_TWP(0xff)) 235 #define CONFIG_SYS_FPGA_FTIM3 0x0 236 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 237 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 238 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 239 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 240 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 241 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 242 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 243 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 244 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT 245 #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR 246 #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK 247 #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR 248 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0 249 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1 250 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2 251 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3 252 253 /* 254 * Serial Port 255 */ 256 #ifdef CONFIG_LPUART 257 #define CONFIG_LPUART_32B_REG 258 #else 259 #define CONFIG_CONS_INDEX 1 260 #define CONFIG_SYS_NS16550_SERIAL 261 #ifndef CONFIG_DM_SERIAL 262 #define CONFIG_SYS_NS16550_REG_SIZE 1 263 #endif 264 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 265 #endif 266 267 /* 268 * I2C 269 */ 270 #define CONFIG_SYS_I2C 271 #define CONFIG_SYS_I2C_MXC 272 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 273 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 274 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 275 276 /* EEPROM */ 277 #define CONFIG_ID_EEPROM 278 #define CONFIG_SYS_I2C_EEPROM_NXID 279 #define CONFIG_SYS_EEPROM_BUS_NUM 1 280 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 281 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 282 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 283 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 284 285 /* 286 * MMC 287 */ 288 #define CONFIG_FSL_ESDHC 289 290 /* SPI */ 291 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 292 /* QSPI */ 293 #define QSPI0_AMBA_BASE 0x40000000 294 #define FSL_QSPI_FLASH_SIZE (1 << 24) 295 #define FSL_QSPI_FLASH_NUM 2 296 297 /* DSPI */ 298 #endif 299 300 /* DM SPI */ 301 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 302 #define CONFIG_DM_SPI_FLASH 303 #endif 304 305 /* 306 * Video 307 */ 308 #define CONFIG_FSL_DCU_FB 309 310 #ifdef CONFIG_FSL_DCU_FB 311 #define CONFIG_CMD_BMP 312 #define CONFIG_VIDEO_LOGO 313 #define CONFIG_VIDEO_BMP_LOGO 314 315 #define CONFIG_FSL_DCU_SII9022A 316 #define CONFIG_SYS_I2C_DVI_BUS_NUM 1 317 #define CONFIG_SYS_I2C_DVI_ADDR 0x39 318 #endif 319 320 /* 321 * eTSEC 322 */ 323 #define CONFIG_TSEC_ENET 324 325 #ifdef CONFIG_TSEC_ENET 326 #define CONFIG_MII 327 #define CONFIG_MII_DEFAULT_TSEC 1 328 #define CONFIG_TSEC1 1 329 #define CONFIG_TSEC1_NAME "eTSEC1" 330 #define CONFIG_TSEC2 1 331 #define CONFIG_TSEC2_NAME "eTSEC2" 332 #define CONFIG_TSEC3 1 333 #define CONFIG_TSEC3_NAME "eTSEC3" 334 335 #define TSEC1_PHY_ADDR 2 336 #define TSEC2_PHY_ADDR 0 337 #define TSEC3_PHY_ADDR 1 338 339 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 340 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 341 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 342 343 #define TSEC1_PHYIDX 0 344 #define TSEC2_PHYIDX 0 345 #define TSEC3_PHYIDX 0 346 347 #define CONFIG_ETHPRIME "eTSEC1" 348 349 #define CONFIG_PHY_GIGE 350 #define CONFIG_PHYLIB 351 #define CONFIG_PHY_ATHEROS 352 353 #define CONFIG_HAS_ETH0 354 #define CONFIG_HAS_ETH1 355 #define CONFIG_HAS_ETH2 356 #endif 357 358 /* PCIe */ 359 #define CONFIG_PCIE1 /* PCIE controller 1 */ 360 #define CONFIG_PCIE2 /* PCIE controller 2 */ 361 362 #ifdef CONFIG_PCI 363 #define CONFIG_PCI_SCAN_SHOW 364 #define CONFIG_CMD_PCI 365 #endif 366 367 #define CONFIG_CMDLINE_TAG 368 #define CONFIG_CMDLINE_EDITING 369 370 #define CONFIG_PEN_ADDR_BIG_ENDIAN 371 #define CONFIG_LAYERSCAPE_NS_ACCESS 372 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 373 #define CONFIG_TIMER_CLK_FREQ 12500000 374 375 #define CONFIG_HWCONFIG 376 #define HWCONFIG_BUFFER_SIZE 256 377 378 #define CONFIG_FSL_DEVICE_DISABLE 379 380 381 #ifdef CONFIG_LPUART 382 #define CONFIG_EXTRA_ENV_SETTINGS \ 383 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ 384 "initrd_high=0xffffffff\0" \ 385 "fdt_high=0xffffffff\0" 386 #else 387 #define CONFIG_EXTRA_ENV_SETTINGS \ 388 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 389 "initrd_high=0xffffffff\0" \ 390 "fdt_high=0xffffffff\0" 391 #endif 392 393 /* 394 * Miscellaneous configurable options 395 */ 396 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 397 #define CONFIG_AUTO_COMPLETE 398 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 399 #define CONFIG_SYS_PBSIZE \ 400 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 401 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 402 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 403 404 #define CONFIG_SYS_MEMTEST_START 0x80000000 405 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 406 407 #define CONFIG_SYS_LOAD_ADDR 0x82000000 408 409 #define CONFIG_LS102XA_STREAM_ID 410 411 /* 412 * Stack sizes 413 * The stack sizes are set up in start.S using the settings below 414 */ 415 #define CONFIG_STACKSIZE (30 * 1024) 416 417 #define CONFIG_SYS_INIT_SP_OFFSET \ 418 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 419 #define CONFIG_SYS_INIT_SP_ADDR \ 420 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 421 422 #ifdef CONFIG_SPL_BUILD 423 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 424 #else 425 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 426 #endif 427 428 #define CONFIG_SYS_QE_FW_ADDR 0x600c0000 429 430 /* 431 * Environment 432 */ 433 #define CONFIG_ENV_OVERWRITE 434 435 #if defined(CONFIG_SD_BOOT) 436 #define CONFIG_ENV_OFFSET 0x100000 437 #define CONFIG_ENV_IS_IN_MMC 438 #define CONFIG_SYS_MMC_ENV_DEV 0 439 #define CONFIG_ENV_SIZE 0x20000 440 #elif defined(CONFIG_QSPI_BOOT) 441 #define CONFIG_ENV_IS_IN_SPI_FLASH 442 #define CONFIG_ENV_SIZE 0x2000 443 #define CONFIG_ENV_OFFSET 0x100000 444 #define CONFIG_ENV_SECT_SIZE 0x10000 445 #else 446 #define CONFIG_ENV_IS_IN_FLASH 447 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 448 #define CONFIG_ENV_SIZE 0x20000 449 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 450 #endif 451 452 #define CONFIG_MISC_INIT_R 453 454 /* Hash command with SHA acceleration supported in hardware */ 455 #ifdef CONFIG_FSL_CAAM 456 #define CONFIG_CMD_HASH 457 #define CONFIG_SHA_HW_ACCEL 458 #endif 459 460 #include <asm/fsl_secure_boot.h> 461 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 462 463 #endif 464