1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_LS102XA 11 12 #define CONFIG_SYS_GENERIC_BOARD 13 14 #define CONFIG_DISPLAY_CPUINFO 15 #define CONFIG_DISPLAY_BOARDINFO 16 17 #define CONFIG_SKIP_LOWLEVEL_INIT 18 #define CONFIG_BOARD_EARLY_INIT_F 19 20 /* 21 * Size of malloc() pool 22 */ 23 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 24 25 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 26 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 27 28 /* 29 * Generic Timer Definitions 30 */ 31 #define GENERIC_TIMER_CLK 12500000 32 33 #define CONFIG_SYS_CLK_FREQ 100000000 34 #define CONFIG_DDR_CLK_FREQ 100000000 35 36 #define DDR_SDRAM_CFG 0x470c0008 37 #define DDR_CS0_BNDS 0x008000bf 38 #define DDR_CS0_CONFIG 0x80014302 39 #define DDR_TIMING_CFG_0 0x50550004 40 #define DDR_TIMING_CFG_1 0xbcb38c56 41 #define DDR_TIMING_CFG_2 0x0040d120 42 #define DDR_TIMING_CFG_3 0x010e1000 43 #define DDR_TIMING_CFG_4 0x00000001 44 #define DDR_TIMING_CFG_5 0x03401400 45 #define DDR_SDRAM_CFG_2 0x00401010 46 #define DDR_SDRAM_MODE 0x00061c60 47 #define DDR_SDRAM_MODE_2 0x00180000 48 #define DDR_SDRAM_INTERVAL 0x18600618 49 #define DDR_DDR_WRLVL_CNTL 0x8655f605 50 #define DDR_DDR_WRLVL_CNTL_2 0x05060607 51 #define DDR_DDR_WRLVL_CNTL_3 0x05050505 52 #define DDR_DDR_CDR1 0x80040000 53 #define DDR_DDR_CDR2 0x00000001 54 #define DDR_SDRAM_CLK_CNTL 0x02000000 55 #define DDR_DDR_ZQ_CNTL 0x89080600 56 #define DDR_CS0_CONFIG_2 0 57 #define DDR_SDRAM_CFG_MEM_EN 0x80000000 58 59 #ifdef CONFIG_RAMBOOT_PBL 60 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg 61 #endif 62 63 #ifdef CONFIG_SD_BOOT 64 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg 65 #define CONFIG_SPL_FRAMEWORK 66 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 67 #define CONFIG_SPL_LIBCOMMON_SUPPORT 68 #define CONFIG_SPL_LIBGENERIC_SUPPORT 69 #define CONFIG_SPL_ENV_SUPPORT 70 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 71 #define CONFIG_SPL_I2C_SUPPORT 72 #define CONFIG_SPL_WATCHDOG_SUPPORT 73 #define CONFIG_SPL_SERIAL_SUPPORT 74 #define CONFIG_SPL_MMC_SUPPORT 75 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 76 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 77 78 #define CONFIG_SPL_TEXT_BASE 0x10000000 79 #define CONFIG_SPL_MAX_SIZE 0x1a000 80 #define CONFIG_SPL_STACK 0x1001d000 81 #define CONFIG_SPL_PAD_TO 0x1c000 82 #define CONFIG_SYS_TEXT_BASE 0x82000000 83 84 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 85 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 86 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 87 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 88 #define CONFIG_SYS_MONITOR_LEN 0x80000 89 #endif 90 91 #ifdef CONFIG_QSPI_BOOT 92 #define CONFIG_SYS_TEXT_BASE 0x40010000 93 #define CONFIG_SYS_NO_FLASH 94 #endif 95 96 #ifndef CONFIG_SYS_TEXT_BASE 97 #define CONFIG_SYS_TEXT_BASE 0x60100000 98 #endif 99 100 #define CONFIG_NR_DRAM_BANKS 1 101 #define PHYS_SDRAM 0x80000000 102 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) 103 104 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 105 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 106 107 #define CONFIG_SYS_HAS_SERDES 108 109 #define CONFIG_FSL_CAAM /* Enable CAAM */ 110 111 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ 112 !defined(CONFIG_QSPI_BOOT) 113 #define CONFIG_U_QE 114 #endif 115 116 /* 117 * IFC Definitions 118 */ 119 #ifndef CONFIG_QSPI_BOOT 120 #define CONFIG_FSL_IFC 121 #define CONFIG_SYS_FLASH_BASE 0x60000000 122 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 123 124 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 125 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 126 CSPR_PORT_SIZE_16 | \ 127 CSPR_MSEL_NOR | \ 128 CSPR_V) 129 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 130 131 /* NOR Flash Timing Params */ 132 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 133 CSOR_NOR_TRHZ_80) 134 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 135 FTIM0_NOR_TEADC(0x5) | \ 136 FTIM0_NOR_TAVDS(0x0) | \ 137 FTIM0_NOR_TEAHC(0x5)) 138 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 139 FTIM1_NOR_TRAD_NOR(0x1A) | \ 140 FTIM1_NOR_TSEQRAD_NOR(0x13)) 141 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 142 FTIM2_NOR_TCH(0x4) | \ 143 FTIM2_NOR_TWP(0x1c) | \ 144 FTIM2_NOR_TWPH(0x0e)) 145 #define CONFIG_SYS_NOR_FTIM3 0 146 147 #define CONFIG_FLASH_CFI_DRIVER 148 #define CONFIG_SYS_FLASH_CFI 149 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 150 #define CONFIG_SYS_FLASH_QUIET_TEST 151 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 152 153 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 154 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 155 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 156 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 157 158 #define CONFIG_SYS_FLASH_EMPTY_INFO 159 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 160 161 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 162 #define CONFIG_SYS_WRITE_SWAPPED_DATA 163 #endif 164 165 /* CPLD */ 166 167 #define CONFIG_SYS_CPLD_BASE 0x7fb00000 168 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 169 170 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 171 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ 172 CSPR_PORT_SIZE_8 | \ 173 CSPR_MSEL_GPCM | \ 174 CSPR_V) 175 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 176 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 177 CSOR_NOR_NOR_MODE_AVD_NOR | \ 178 CSOR_NOR_TRHZ_80) 179 180 /* CPLD Timing parameters for IFC GPCM */ 181 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ 182 FTIM0_GPCM_TEADC(0xf) | \ 183 FTIM0_GPCM_TEAHC(0xf)) 184 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 185 FTIM1_GPCM_TRAD(0x3f)) 186 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 187 FTIM2_GPCM_TCH(0xf) | \ 188 FTIM2_GPCM_TWP(0xff)) 189 #define CONFIG_SYS_FPGA_FTIM3 0x0 190 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 191 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 192 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 193 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 194 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 195 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 196 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 197 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 198 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT 199 #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR 200 #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK 201 #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR 202 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0 203 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1 204 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2 205 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3 206 207 /* 208 * Serial Port 209 */ 210 #ifdef CONFIG_LPUART 211 #define CONFIG_FSL_LPUART 212 #define CONFIG_LPUART_32B_REG 213 #else 214 #define CONFIG_CONS_INDEX 1 215 #define CONFIG_SYS_NS16550 216 #define CONFIG_SYS_NS16550_SERIAL 217 #define CONFIG_SYS_NS16550_REG_SIZE 1 218 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 219 #endif 220 221 #define CONFIG_BAUDRATE 115200 222 223 /* 224 * I2C 225 */ 226 #define CONFIG_CMD_I2C 227 #define CONFIG_SYS_I2C 228 #define CONFIG_SYS_I2C_MXC 229 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 230 231 /* EEPROM */ 232 #ifndef CONFIG_SD_BOOT 233 #define CONFIG_ID_EEPROM 234 #define CONFIG_SYS_I2C_EEPROM_NXID 235 #define CONFIG_SYS_EEPROM_BUS_NUM 1 236 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 237 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 238 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 239 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 240 #endif 241 242 /* 243 * MMC 244 */ 245 #define CONFIG_MMC 246 #define CONFIG_CMD_MMC 247 #define CONFIG_FSL_ESDHC 248 #define CONFIG_GENERIC_MMC 249 250 #define CONFIG_CMD_FAT 251 #define CONFIG_DOS_PARTITION 252 253 /* SPI */ 254 #ifdef CONFIG_QSPI_BOOT 255 /* QSPI */ 256 #define CONFIG_FSL_QSPI 257 #define QSPI0_AMBA_BASE 0x40000000 258 #define FSL_QSPI_FLASH_SIZE (1 << 24) 259 #define FSL_QSPI_FLASH_NUM 2 260 #define CONFIG_SPI_FLASH_STMICRO 261 262 /* DM SPI */ 263 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 264 #define CONFIG_CMD_SF 265 #define CONFIG_DM_SPI_FLASH 266 #endif 267 #endif 268 269 /* 270 * Video 271 */ 272 #define CONFIG_FSL_DCU_FB 273 274 #ifdef CONFIG_FSL_DCU_FB 275 #define CONFIG_VIDEO 276 #define CONFIG_CMD_BMP 277 #define CONFIG_CFB_CONSOLE 278 #define CONFIG_VGA_AS_SINGLE_DEVICE 279 #define CONFIG_VIDEO_LOGO 280 #define CONFIG_VIDEO_BMP_LOGO 281 282 #define CONFIG_FSL_DCU_SII9022A 283 #define CONFIG_SYS_I2C_DVI_BUS_NUM 1 284 #define CONFIG_SYS_I2C_DVI_ADDR 0x39 285 #endif 286 287 /* 288 * eTSEC 289 */ 290 #define CONFIG_TSEC_ENET 291 292 #ifdef CONFIG_TSEC_ENET 293 #define CONFIG_MII 294 #define CONFIG_MII_DEFAULT_TSEC 1 295 #define CONFIG_TSEC1 1 296 #define CONFIG_TSEC1_NAME "eTSEC1" 297 #define CONFIG_TSEC2 1 298 #define CONFIG_TSEC2_NAME "eTSEC2" 299 #define CONFIG_TSEC3 1 300 #define CONFIG_TSEC3_NAME "eTSEC3" 301 302 #define TSEC1_PHY_ADDR 2 303 #define TSEC2_PHY_ADDR 0 304 #define TSEC3_PHY_ADDR 1 305 306 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 307 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 308 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 309 310 #define TSEC1_PHYIDX 0 311 #define TSEC2_PHYIDX 0 312 #define TSEC3_PHYIDX 0 313 314 #define CONFIG_ETHPRIME "eTSEC1" 315 316 #define CONFIG_PHY_GIGE 317 #define CONFIG_PHYLIB 318 #define CONFIG_PHY_ATHEROS 319 320 #define CONFIG_HAS_ETH0 321 #define CONFIG_HAS_ETH1 322 #define CONFIG_HAS_ETH2 323 #endif 324 325 /* PCIe */ 326 #define CONFIG_PCI /* Enable PCI/PCIE */ 327 #define CONFIG_PCIE1 /* PCIE controler 1 */ 328 #define CONFIG_PCIE2 /* PCIE controler 2 */ 329 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 330 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" 331 332 #define CONFIG_SYS_PCI_64BIT 333 334 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 335 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ 336 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 337 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ 338 339 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 340 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 341 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ 342 343 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 344 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 345 #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ 346 347 #ifdef CONFIG_PCI 348 #define CONFIG_PCI_PNP 349 #define CONFIG_E1000 350 #define CONFIG_PCI_SCAN_SHOW 351 #define CONFIG_CMD_PCI 352 #endif 353 354 #define CONFIG_CMD_PING 355 #define CONFIG_CMD_DHCP 356 #define CONFIG_CMD_MII 357 358 #define CONFIG_CMDLINE_TAG 359 #define CONFIG_CMDLINE_EDITING 360 361 #define CONFIG_ARMV7_NONSEC 362 #define CONFIG_ARMV7_VIRT 363 #define CONFIG_PEN_ADDR_BIG_ENDIAN 364 #define CONFIG_LS102XA_NS_ACCESS 365 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 366 #define CONFIG_TIMER_CLK_FREQ 12500000 367 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 368 369 #define CONFIG_HWCONFIG 370 #define HWCONFIG_BUFFER_SIZE 128 371 372 #define CONFIG_BOOTDELAY 3 373 374 #ifdef CONFIG_LPUART 375 #define CONFIG_EXTRA_ENV_SETTINGS \ 376 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ 377 "initrd_high=0xcfffffff\0" \ 378 "fdt_high=0xcfffffff\0" 379 #else 380 #define CONFIG_EXTRA_ENV_SETTINGS \ 381 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 382 "initrd_high=0xcfffffff\0" \ 383 "fdt_high=0xcfffffff\0" 384 #endif 385 386 /* 387 * Miscellaneous configurable options 388 */ 389 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 390 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 391 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 392 #define CONFIG_AUTO_COMPLETE 393 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 394 #define CONFIG_SYS_PBSIZE \ 395 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 396 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 397 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 398 399 #define CONFIG_CMD_GREPENV 400 #define CONFIG_CMD_MEMINFO 401 #define CONFIG_CMD_MEMTEST 402 #define CONFIG_SYS_MEMTEST_START 0x80000000 403 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 404 405 #define CONFIG_SYS_LOAD_ADDR 0x82000000 406 407 #define CONFIG_LS102XA_STREAM_ID 408 409 /* 410 * Stack sizes 411 * The stack sizes are set up in start.S using the settings below 412 */ 413 #define CONFIG_STACKSIZE (30 * 1024) 414 415 #define CONFIG_SYS_INIT_SP_OFFSET \ 416 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 417 #define CONFIG_SYS_INIT_SP_ADDR \ 418 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 419 420 #ifdef CONFIG_SPL_BUILD 421 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 422 #else 423 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 424 #endif 425 426 #define CONFIG_SYS_QE_FW_ADDR 0x67f40000 427 428 /* 429 * Environment 430 */ 431 #define CONFIG_ENV_OVERWRITE 432 433 #if defined(CONFIG_SD_BOOT) 434 #define CONFIG_ENV_OFFSET 0x100000 435 #define CONFIG_ENV_IS_IN_MMC 436 #define CONFIG_SYS_MMC_ENV_DEV 0 437 #define CONFIG_ENV_SIZE 0x20000 438 #elif defined(CONFIG_QSPI_BOOT) 439 #define CONFIG_ENV_IS_IN_SPI_FLASH 440 #define CONFIG_ENV_SIZE 0x2000 441 #define CONFIG_ENV_OFFSET 0x100000 442 #define CONFIG_ENV_SECT_SIZE 0x10000 443 #else 444 #define CONFIG_ENV_IS_IN_FLASH 445 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 446 #define CONFIG_ENV_SIZE 0x20000 447 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 448 #endif 449 450 #define CONFIG_OF_LIBFDT 451 #define CONFIG_OF_BOARD_SETUP 452 #define CONFIG_CMD_BOOTZ 453 454 #define CONFIG_MISC_INIT_R 455 456 /* Hash command with SHA acceleration supported in hardware */ 457 #define CONFIG_CMD_HASH 458 #define CONFIG_SHA_HW_ACCEL 459 460 #ifdef CONFIG_SECURE_BOOT 461 #define CONFIG_CMD_BLOB 462 #endif 463 464 #endif 465