1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_LS102XA 11 12 #define CONFIG_ARMV7_PSCI_1_0 13 14 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 15 16 #define CONFIG_SYS_FSL_CLK 17 18 #define CONFIG_SKIP_LOWLEVEL_INIT 19 #define CONFIG_BOARD_EARLY_INIT_F 20 #define CONFIG_DEEP_SLEEP 21 22 /* 23 * Size of malloc() pool 24 */ 25 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 26 27 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 28 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 29 30 /* 31 * USB 32 */ 33 34 /* 35 * EHCI Support - disbaled by default as 36 * there is no signal coming out of soc on 37 * this board for this controller. However, 38 * the silicon still has this controller, 39 * and anyone can use this controller by 40 * taking signals out on their board. 41 */ 42 43 /*#define CONFIG_HAS_FSL_DR_USB*/ 44 45 #ifdef CONFIG_HAS_FSL_DR_USB 46 #define CONFIG_USB_EHCI 47 #define CONFIG_USB_EHCI_FSL 48 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 49 #endif 50 51 /* XHCI Support - enabled by default */ 52 #define CONFIG_HAS_FSL_XHCI_USB 53 54 #ifdef CONFIG_HAS_FSL_XHCI_USB 55 #define CONFIG_USB_XHCI_FSL 56 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 57 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 58 #endif 59 60 /* 61 * Generic Timer Definitions 62 */ 63 #define GENERIC_TIMER_CLK 12500000 64 65 #define CONFIG_SYS_CLK_FREQ 100000000 66 #define CONFIG_DDR_CLK_FREQ 100000000 67 68 #define DDR_SDRAM_CFG 0x470c0008 69 #define DDR_CS0_BNDS 0x008000bf 70 #define DDR_CS0_CONFIG 0x80014302 71 #define DDR_TIMING_CFG_0 0x50550004 72 #define DDR_TIMING_CFG_1 0xbcb38c56 73 #define DDR_TIMING_CFG_2 0x0040d120 74 #define DDR_TIMING_CFG_3 0x010e1000 75 #define DDR_TIMING_CFG_4 0x00000001 76 #define DDR_TIMING_CFG_5 0x03401400 77 #define DDR_SDRAM_CFG_2 0x00401010 78 #define DDR_SDRAM_MODE 0x00061c60 79 #define DDR_SDRAM_MODE_2 0x00180000 80 #define DDR_SDRAM_INTERVAL 0x18600618 81 #define DDR_DDR_WRLVL_CNTL 0x8655f605 82 #define DDR_DDR_WRLVL_CNTL_2 0x05060607 83 #define DDR_DDR_WRLVL_CNTL_3 0x05050505 84 #define DDR_DDR_CDR1 0x80040000 85 #define DDR_DDR_CDR2 0x00000001 86 #define DDR_SDRAM_CLK_CNTL 0x02000000 87 #define DDR_DDR_ZQ_CNTL 0x89080600 88 #define DDR_CS0_CONFIG_2 0 89 #define DDR_SDRAM_CFG_MEM_EN 0x80000000 90 #define SDRAM_CFG2_D_INIT 0x00000010 91 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080 92 #define SDRAM_CFG2_FRC_SR 0x80000000 93 #define SDRAM_CFG_BI 0x00000001 94 95 #ifdef CONFIG_RAMBOOT_PBL 96 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg 97 #endif 98 99 #ifdef CONFIG_SD_BOOT 100 #ifdef CONFIG_SD_BOOT_QSPI 101 #define CONFIG_SYS_FSL_PBL_RCW \ 102 board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg 103 #else 104 #define CONFIG_SYS_FSL_PBL_RCW \ 105 board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg 106 #endif 107 #define CONFIG_SPL_FRAMEWORK 108 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 109 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 110 111 #ifdef CONFIG_SECURE_BOOT 112 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 113 /* 114 * HDR would be appended at end of image and copied to DDR along 115 * with U-Boot image. 116 */ 117 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS (0x400 + \ 118 (CONFIG_U_BOOT_HDR_SIZE / 512) 119 #else 120 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 121 #endif /* ifdef CONFIG_SECURE_BOOT */ 122 123 #define CONFIG_SPL_TEXT_BASE 0x10000000 124 #define CONFIG_SPL_MAX_SIZE 0x1a000 125 #define CONFIG_SPL_STACK 0x1001d000 126 #define CONFIG_SPL_PAD_TO 0x1c000 127 #define CONFIG_SYS_TEXT_BASE 0x82000000 128 129 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 130 CONFIG_SYS_MONITOR_LEN) 131 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 132 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 133 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 134 135 #ifdef CONFIG_U_BOOT_HDR_SIZE 136 /* 137 * HDR would be appended at end of image and copied to DDR along 138 * with U-Boot image. Here u-boot max. size is 512K. So if binary 139 * size increases then increase this size in case of secure boot as 140 * it uses raw u-boot image instead of fit image. 141 */ 142 #define CONFIG_SYS_MONITOR_LEN (0x80000 + CONFIG_U_BOOT_HDR_SIZE) 143 #else 144 #define CONFIG_SYS_MONITOR_LEN 0x80000 145 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ 146 #endif 147 148 #ifdef CONFIG_QSPI_BOOT 149 #define CONFIG_SYS_TEXT_BASE 0x40010000 150 #endif 151 152 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 153 #define CONFIG_SYS_NO_FLASH 154 #endif 155 156 #ifndef CONFIG_SYS_TEXT_BASE 157 #define CONFIG_SYS_TEXT_BASE 0x60100000 158 #endif 159 160 #define CONFIG_NR_DRAM_BANKS 1 161 #define PHYS_SDRAM 0x80000000 162 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) 163 164 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 165 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 166 167 #define CONFIG_FSL_CAAM /* Enable CAAM */ 168 169 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ 170 !defined(CONFIG_QSPI_BOOT) 171 #define CONFIG_U_QE 172 #endif 173 174 /* 175 * IFC Definitions 176 */ 177 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 178 #define CONFIG_FSL_IFC 179 #define CONFIG_SYS_FLASH_BASE 0x60000000 180 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 181 182 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 183 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 184 CSPR_PORT_SIZE_16 | \ 185 CSPR_MSEL_NOR | \ 186 CSPR_V) 187 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 188 189 /* NOR Flash Timing Params */ 190 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 191 CSOR_NOR_TRHZ_80) 192 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 193 FTIM0_NOR_TEADC(0x5) | \ 194 FTIM0_NOR_TAVDS(0x0) | \ 195 FTIM0_NOR_TEAHC(0x5)) 196 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 197 FTIM1_NOR_TRAD_NOR(0x1A) | \ 198 FTIM1_NOR_TSEQRAD_NOR(0x13)) 199 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 200 FTIM2_NOR_TCH(0x4) | \ 201 FTIM2_NOR_TWP(0x1c) | \ 202 FTIM2_NOR_TWPH(0x0e)) 203 #define CONFIG_SYS_NOR_FTIM3 0 204 205 #define CONFIG_FLASH_CFI_DRIVER 206 #define CONFIG_SYS_FLASH_CFI 207 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 208 #define CONFIG_SYS_FLASH_QUIET_TEST 209 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 210 211 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 212 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 213 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 214 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 215 216 #define CONFIG_SYS_FLASH_EMPTY_INFO 217 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 218 219 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 220 #define CONFIG_SYS_WRITE_SWAPPED_DATA 221 #endif 222 223 /* CPLD */ 224 225 #define CONFIG_SYS_CPLD_BASE 0x7fb00000 226 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 227 228 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 229 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ 230 CSPR_PORT_SIZE_8 | \ 231 CSPR_MSEL_GPCM | \ 232 CSPR_V) 233 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 234 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 235 CSOR_NOR_NOR_MODE_AVD_NOR | \ 236 CSOR_NOR_TRHZ_80) 237 238 /* CPLD Timing parameters for IFC GPCM */ 239 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ 240 FTIM0_GPCM_TEADC(0xf) | \ 241 FTIM0_GPCM_TEAHC(0xf)) 242 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 243 FTIM1_GPCM_TRAD(0x3f)) 244 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 245 FTIM2_GPCM_TCH(0xf) | \ 246 FTIM2_GPCM_TWP(0xff)) 247 #define CONFIG_SYS_FPGA_FTIM3 0x0 248 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 249 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 250 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 251 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 252 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 253 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 254 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 255 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 256 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT 257 #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR 258 #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK 259 #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR 260 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0 261 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1 262 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2 263 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3 264 265 /* 266 * Serial Port 267 */ 268 #ifdef CONFIG_LPUART 269 #define CONFIG_LPUART_32B_REG 270 #else 271 #define CONFIG_CONS_INDEX 1 272 #define CONFIG_SYS_NS16550_SERIAL 273 #ifndef CONFIG_DM_SERIAL 274 #define CONFIG_SYS_NS16550_REG_SIZE 1 275 #endif 276 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 277 #endif 278 279 #define CONFIG_BAUDRATE 115200 280 281 /* 282 * I2C 283 */ 284 #define CONFIG_SYS_I2C 285 #define CONFIG_SYS_I2C_MXC 286 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 287 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 288 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 289 290 /* EEPROM */ 291 #define CONFIG_ID_EEPROM 292 #define CONFIG_SYS_I2C_EEPROM_NXID 293 #define CONFIG_SYS_EEPROM_BUS_NUM 1 294 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 295 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 296 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 297 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 298 299 /* 300 * MMC 301 */ 302 #define CONFIG_MMC 303 #define CONFIG_FSL_ESDHC 304 #define CONFIG_GENERIC_MMC 305 306 #define CONFIG_DOS_PARTITION 307 308 /* SPI */ 309 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 310 /* QSPI */ 311 #define QSPI0_AMBA_BASE 0x40000000 312 #define FSL_QSPI_FLASH_SIZE (1 << 24) 313 #define FSL_QSPI_FLASH_NUM 2 314 315 /* DSPI */ 316 #endif 317 318 /* DM SPI */ 319 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 320 #define CONFIG_DM_SPI_FLASH 321 #endif 322 323 /* 324 * Video 325 */ 326 #define CONFIG_FSL_DCU_FB 327 328 #ifdef CONFIG_FSL_DCU_FB 329 #define CONFIG_CMD_BMP 330 #define CONFIG_VIDEO_LOGO 331 #define CONFIG_VIDEO_BMP_LOGO 332 333 #define CONFIG_FSL_DCU_SII9022A 334 #define CONFIG_SYS_I2C_DVI_BUS_NUM 1 335 #define CONFIG_SYS_I2C_DVI_ADDR 0x39 336 #endif 337 338 /* 339 * eTSEC 340 */ 341 #define CONFIG_TSEC_ENET 342 343 #ifdef CONFIG_TSEC_ENET 344 #define CONFIG_MII 345 #define CONFIG_MII_DEFAULT_TSEC 1 346 #define CONFIG_TSEC1 1 347 #define CONFIG_TSEC1_NAME "eTSEC1" 348 #define CONFIG_TSEC2 1 349 #define CONFIG_TSEC2_NAME "eTSEC2" 350 #define CONFIG_TSEC3 1 351 #define CONFIG_TSEC3_NAME "eTSEC3" 352 353 #define TSEC1_PHY_ADDR 2 354 #define TSEC2_PHY_ADDR 0 355 #define TSEC3_PHY_ADDR 1 356 357 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 358 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 359 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 360 361 #define TSEC1_PHYIDX 0 362 #define TSEC2_PHYIDX 0 363 #define TSEC3_PHYIDX 0 364 365 #define CONFIG_ETHPRIME "eTSEC1" 366 367 #define CONFIG_PHY_GIGE 368 #define CONFIG_PHYLIB 369 #define CONFIG_PHY_ATHEROS 370 371 #define CONFIG_HAS_ETH0 372 #define CONFIG_HAS_ETH1 373 #define CONFIG_HAS_ETH2 374 #endif 375 376 /* PCIe */ 377 #define CONFIG_PCIE1 /* PCIE controller 1 */ 378 #define CONFIG_PCIE2 /* PCIE controller 2 */ 379 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 380 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" 381 382 #define CONFIG_SYS_PCI_64BIT 383 384 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 385 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ 386 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 387 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ 388 389 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 390 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 391 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ 392 393 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 394 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 395 #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ 396 397 #ifdef CONFIG_PCI 398 #define CONFIG_PCI_SCAN_SHOW 399 #define CONFIG_CMD_PCI 400 #endif 401 402 #define CONFIG_CMDLINE_TAG 403 #define CONFIG_CMDLINE_EDITING 404 405 #define CONFIG_PEN_ADDR_BIG_ENDIAN 406 #define CONFIG_LAYERSCAPE_NS_ACCESS 407 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 408 #define CONFIG_TIMER_CLK_FREQ 12500000 409 410 #define CONFIG_HWCONFIG 411 #define HWCONFIG_BUFFER_SIZE 256 412 413 #define CONFIG_FSL_DEVICE_DISABLE 414 415 416 #ifdef CONFIG_LPUART 417 #define CONFIG_EXTRA_ENV_SETTINGS \ 418 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ 419 "initrd_high=0xffffffff\0" \ 420 "fdt_high=0xffffffff\0" 421 #else 422 #define CONFIG_EXTRA_ENV_SETTINGS \ 423 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 424 "initrd_high=0xffffffff\0" \ 425 "fdt_high=0xffffffff\0" 426 #endif 427 428 /* 429 * Miscellaneous configurable options 430 */ 431 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 432 #define CONFIG_AUTO_COMPLETE 433 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 434 #define CONFIG_SYS_PBSIZE \ 435 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 436 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 437 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 438 439 #define CONFIG_SYS_MEMTEST_START 0x80000000 440 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 441 442 #define CONFIG_SYS_LOAD_ADDR 0x82000000 443 444 #define CONFIG_LS102XA_STREAM_ID 445 446 /* 447 * Stack sizes 448 * The stack sizes are set up in start.S using the settings below 449 */ 450 #define CONFIG_STACKSIZE (30 * 1024) 451 452 #define CONFIG_SYS_INIT_SP_OFFSET \ 453 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 454 #define CONFIG_SYS_INIT_SP_ADDR \ 455 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 456 457 #ifdef CONFIG_SPL_BUILD 458 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 459 #else 460 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 461 #endif 462 463 #define CONFIG_SYS_QE_FW_ADDR 0x600c0000 464 465 /* 466 * Environment 467 */ 468 #define CONFIG_ENV_OVERWRITE 469 470 #if defined(CONFIG_SD_BOOT) 471 #define CONFIG_ENV_OFFSET 0x100000 472 #define CONFIG_ENV_IS_IN_MMC 473 #define CONFIG_SYS_MMC_ENV_DEV 0 474 #define CONFIG_ENV_SIZE 0x20000 475 #elif defined(CONFIG_QSPI_BOOT) 476 #define CONFIG_ENV_IS_IN_SPI_FLASH 477 #define CONFIG_ENV_SIZE 0x2000 478 #define CONFIG_ENV_OFFSET 0x100000 479 #define CONFIG_ENV_SECT_SIZE 0x10000 480 #else 481 #define CONFIG_ENV_IS_IN_FLASH 482 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 483 #define CONFIG_ENV_SIZE 0x20000 484 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 485 #endif 486 487 #define CONFIG_MISC_INIT_R 488 489 /* Hash command with SHA acceleration supported in hardware */ 490 #ifdef CONFIG_FSL_CAAM 491 #define CONFIG_CMD_HASH 492 #define CONFIG_SHA_HW_ACCEL 493 #endif 494 495 #include <asm/fsl_secure_boot.h> 496 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 497 498 #endif 499