1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_LS102XA 11 12 #define CONFIG_ARMV7_PSCI 13 #define CONFIG_ARMV7_PSCI_NR_CPUS CONFIG_MAX_CPUS 14 15 #define CONFIG_SYS_FSL_CLK 16 17 #define CONFIG_DISPLAY_CPUINFO 18 #define CONFIG_DISPLAY_BOARDINFO 19 20 #define CONFIG_SKIP_LOWLEVEL_INIT 21 #define CONFIG_BOARD_EARLY_INIT_F 22 #define CONFIG_DEEP_SLEEP 23 #ifdef CONFIG_DEEP_SLEEP 24 #define CONFIG_SILENT_CONSOLE 25 #endif 26 27 /* 28 * Size of malloc() pool 29 */ 30 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 31 32 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 33 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 34 35 /* 36 * USB 37 */ 38 39 /* 40 * EHCI Support - disbaled by default as 41 * there is no signal coming out of soc on 42 * this board for this controller. However, 43 * the silicon still has this controller, 44 * and anyone can use this controller by 45 * taking signals out on their board. 46 */ 47 48 /*#define CONFIG_HAS_FSL_DR_USB*/ 49 50 #ifdef CONFIG_HAS_FSL_DR_USB 51 #define CONFIG_USB_EHCI 52 #define CONFIG_USB_EHCI_FSL 53 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 54 #endif 55 56 /* XHCI Support - enabled by default */ 57 #define CONFIG_HAS_FSL_XHCI_USB 58 59 #ifdef CONFIG_HAS_FSL_XHCI_USB 60 #define CONFIG_USB_XHCI_FSL 61 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 62 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 63 #endif 64 65 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB) 66 #define CONFIG_USB_STORAGE 67 #endif 68 69 /* 70 * Generic Timer Definitions 71 */ 72 #define GENERIC_TIMER_CLK 12500000 73 74 #define CONFIG_SYS_CLK_FREQ 100000000 75 #define CONFIG_DDR_CLK_FREQ 100000000 76 77 #define DDR_SDRAM_CFG 0x470c0008 78 #define DDR_CS0_BNDS 0x008000bf 79 #define DDR_CS0_CONFIG 0x80014302 80 #define DDR_TIMING_CFG_0 0x50550004 81 #define DDR_TIMING_CFG_1 0xbcb38c56 82 #define DDR_TIMING_CFG_2 0x0040d120 83 #define DDR_TIMING_CFG_3 0x010e1000 84 #define DDR_TIMING_CFG_4 0x00000001 85 #define DDR_TIMING_CFG_5 0x03401400 86 #define DDR_SDRAM_CFG_2 0x00401010 87 #define DDR_SDRAM_MODE 0x00061c60 88 #define DDR_SDRAM_MODE_2 0x00180000 89 #define DDR_SDRAM_INTERVAL 0x18600618 90 #define DDR_DDR_WRLVL_CNTL 0x8655f605 91 #define DDR_DDR_WRLVL_CNTL_2 0x05060607 92 #define DDR_DDR_WRLVL_CNTL_3 0x05050505 93 #define DDR_DDR_CDR1 0x80040000 94 #define DDR_DDR_CDR2 0x00000001 95 #define DDR_SDRAM_CLK_CNTL 0x02000000 96 #define DDR_DDR_ZQ_CNTL 0x89080600 97 #define DDR_CS0_CONFIG_2 0 98 #define DDR_SDRAM_CFG_MEM_EN 0x80000000 99 #define SDRAM_CFG2_D_INIT 0x00000010 100 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080 101 #define SDRAM_CFG2_FRC_SR 0x80000000 102 #define SDRAM_CFG_BI 0x00000001 103 104 #ifdef CONFIG_RAMBOOT_PBL 105 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg 106 #endif 107 108 #ifdef CONFIG_SD_BOOT 109 #ifdef CONFIG_SD_BOOT_QSPI 110 #define CONFIG_SYS_FSL_PBL_RCW \ 111 board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg 112 #else 113 #define CONFIG_SYS_FSL_PBL_RCW \ 114 board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg 115 #endif 116 #define CONFIG_SPL_FRAMEWORK 117 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 118 #define CONFIG_SPL_LIBCOMMON_SUPPORT 119 #define CONFIG_SPL_LIBGENERIC_SUPPORT 120 #define CONFIG_SPL_ENV_SUPPORT 121 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 122 #define CONFIG_SPL_I2C_SUPPORT 123 #define CONFIG_SPL_WATCHDOG_SUPPORT 124 #define CONFIG_SPL_SERIAL_SUPPORT 125 #define CONFIG_SPL_MMC_SUPPORT 126 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 127 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 128 129 #define CONFIG_SPL_TEXT_BASE 0x10000000 130 #define CONFIG_SPL_MAX_SIZE 0x1a000 131 #define CONFIG_SPL_STACK 0x1001d000 132 #define CONFIG_SPL_PAD_TO 0x1c000 133 #define CONFIG_SYS_TEXT_BASE 0x82000000 134 135 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 136 CONFIG_SYS_MONITOR_LEN) 137 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 138 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 139 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 140 #define CONFIG_SYS_MONITOR_LEN 0x80000 141 #endif 142 143 #ifdef CONFIG_QSPI_BOOT 144 #define CONFIG_SYS_TEXT_BASE 0x40010000 145 #endif 146 147 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 148 #define CONFIG_SYS_NO_FLASH 149 #endif 150 151 #ifndef CONFIG_SYS_TEXT_BASE 152 #define CONFIG_SYS_TEXT_BASE 0x60100000 153 #endif 154 155 #define CONFIG_NR_DRAM_BANKS 1 156 #define PHYS_SDRAM 0x80000000 157 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) 158 159 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 160 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 161 162 #define CONFIG_SYS_HAS_SERDES 163 164 #define CONFIG_FSL_CAAM /* Enable CAAM */ 165 166 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ 167 !defined(CONFIG_QSPI_BOOT) 168 #define CONFIG_U_QE 169 #endif 170 171 /* 172 * IFC Definitions 173 */ 174 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 175 #define CONFIG_FSL_IFC 176 #define CONFIG_SYS_FLASH_BASE 0x60000000 177 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 178 179 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 180 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 181 CSPR_PORT_SIZE_16 | \ 182 CSPR_MSEL_NOR | \ 183 CSPR_V) 184 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 185 186 /* NOR Flash Timing Params */ 187 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 188 CSOR_NOR_TRHZ_80) 189 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 190 FTIM0_NOR_TEADC(0x5) | \ 191 FTIM0_NOR_TAVDS(0x0) | \ 192 FTIM0_NOR_TEAHC(0x5)) 193 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 194 FTIM1_NOR_TRAD_NOR(0x1A) | \ 195 FTIM1_NOR_TSEQRAD_NOR(0x13)) 196 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 197 FTIM2_NOR_TCH(0x4) | \ 198 FTIM2_NOR_TWP(0x1c) | \ 199 FTIM2_NOR_TWPH(0x0e)) 200 #define CONFIG_SYS_NOR_FTIM3 0 201 202 #define CONFIG_FLASH_CFI_DRIVER 203 #define CONFIG_SYS_FLASH_CFI 204 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 205 #define CONFIG_SYS_FLASH_QUIET_TEST 206 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 207 208 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 209 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 210 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 211 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 212 213 #define CONFIG_SYS_FLASH_EMPTY_INFO 214 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 215 216 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 217 #define CONFIG_SYS_WRITE_SWAPPED_DATA 218 #endif 219 220 /* CPLD */ 221 222 #define CONFIG_SYS_CPLD_BASE 0x7fb00000 223 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 224 225 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 226 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ 227 CSPR_PORT_SIZE_8 | \ 228 CSPR_MSEL_GPCM | \ 229 CSPR_V) 230 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 231 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 232 CSOR_NOR_NOR_MODE_AVD_NOR | \ 233 CSOR_NOR_TRHZ_80) 234 235 /* CPLD Timing parameters for IFC GPCM */ 236 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ 237 FTIM0_GPCM_TEADC(0xf) | \ 238 FTIM0_GPCM_TEAHC(0xf)) 239 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 240 FTIM1_GPCM_TRAD(0x3f)) 241 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 242 FTIM2_GPCM_TCH(0xf) | \ 243 FTIM2_GPCM_TWP(0xff)) 244 #define CONFIG_SYS_FPGA_FTIM3 0x0 245 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 246 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 247 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 248 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 249 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 250 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 251 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 252 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 253 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT 254 #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR 255 #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK 256 #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR 257 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0 258 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1 259 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2 260 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3 261 262 /* 263 * Serial Port 264 */ 265 #ifdef CONFIG_LPUART 266 #define CONFIG_LPUART_32B_REG 267 #else 268 #define CONFIG_CONS_INDEX 1 269 #define CONFIG_SYS_NS16550_SERIAL 270 #ifndef CONFIG_DM_SERIAL 271 #define CONFIG_SYS_NS16550_REG_SIZE 1 272 #endif 273 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 274 #endif 275 276 #define CONFIG_BAUDRATE 115200 277 278 /* 279 * I2C 280 */ 281 #define CONFIG_SYS_I2C 282 #define CONFIG_SYS_I2C_MXC 283 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 284 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 285 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 286 287 /* EEPROM */ 288 #define CONFIG_ID_EEPROM 289 #define CONFIG_SYS_I2C_EEPROM_NXID 290 #define CONFIG_SYS_EEPROM_BUS_NUM 1 291 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 292 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 293 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 294 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 295 296 /* 297 * MMC 298 */ 299 #define CONFIG_MMC 300 #define CONFIG_FSL_ESDHC 301 #define CONFIG_GENERIC_MMC 302 303 #define CONFIG_DOS_PARTITION 304 305 /* SPI */ 306 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 307 /* QSPI */ 308 #define QSPI0_AMBA_BASE 0x40000000 309 #define FSL_QSPI_FLASH_SIZE (1 << 24) 310 #define FSL_QSPI_FLASH_NUM 2 311 312 /* DSPI */ 313 #endif 314 315 /* DM SPI */ 316 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 317 #define CONFIG_DM_SPI_FLASH 318 #endif 319 320 /* 321 * Video 322 */ 323 #define CONFIG_FSL_DCU_FB 324 325 #ifdef CONFIG_FSL_DCU_FB 326 #define CONFIG_VIDEO 327 #define CONFIG_CMD_BMP 328 #define CONFIG_CFB_CONSOLE 329 #define CONFIG_VGA_AS_SINGLE_DEVICE 330 #define CONFIG_VIDEO_LOGO 331 #define CONFIG_VIDEO_BMP_LOGO 332 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 333 334 #define CONFIG_FSL_DCU_SII9022A 335 #define CONFIG_SYS_I2C_DVI_BUS_NUM 1 336 #define CONFIG_SYS_I2C_DVI_ADDR 0x39 337 #endif 338 339 /* 340 * eTSEC 341 */ 342 #define CONFIG_TSEC_ENET 343 344 #ifdef CONFIG_TSEC_ENET 345 #define CONFIG_MII 346 #define CONFIG_MII_DEFAULT_TSEC 1 347 #define CONFIG_TSEC1 1 348 #define CONFIG_TSEC1_NAME "eTSEC1" 349 #define CONFIG_TSEC2 1 350 #define CONFIG_TSEC2_NAME "eTSEC2" 351 #define CONFIG_TSEC3 1 352 #define CONFIG_TSEC3_NAME "eTSEC3" 353 354 #define TSEC1_PHY_ADDR 2 355 #define TSEC2_PHY_ADDR 0 356 #define TSEC3_PHY_ADDR 1 357 358 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 359 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 360 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 361 362 #define TSEC1_PHYIDX 0 363 #define TSEC2_PHYIDX 0 364 #define TSEC3_PHYIDX 0 365 366 #define CONFIG_ETHPRIME "eTSEC1" 367 368 #define CONFIG_PHY_GIGE 369 #define CONFIG_PHYLIB 370 #define CONFIG_PHY_ATHEROS 371 372 #define CONFIG_HAS_ETH0 373 #define CONFIG_HAS_ETH1 374 #define CONFIG_HAS_ETH2 375 #endif 376 377 /* PCIe */ 378 #define CONFIG_PCI /* Enable PCI/PCIE */ 379 #define CONFIG_PCIE1 /* PCIE controller 1 */ 380 #define CONFIG_PCIE2 /* PCIE controller 2 */ 381 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 382 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" 383 384 #define CONFIG_SYS_PCI_64BIT 385 386 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 387 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ 388 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 389 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ 390 391 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 392 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 393 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ 394 395 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 396 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 397 #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ 398 399 #ifdef CONFIG_PCI 400 #define CONFIG_PCI_PNP 401 #define CONFIG_PCI_SCAN_SHOW 402 #define CONFIG_CMD_PCI 403 #endif 404 405 #define CONFIG_CMDLINE_TAG 406 #define CONFIG_CMDLINE_EDITING 407 408 #define CONFIG_ARMV7_NONSEC 409 #define CONFIG_ARMV7_VIRT 410 #define CONFIG_PEN_ADDR_BIG_ENDIAN 411 #define CONFIG_LAYERSCAPE_NS_ACCESS 412 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 413 #define CONFIG_TIMER_CLK_FREQ 12500000 414 415 #define CONFIG_HWCONFIG 416 #define HWCONFIG_BUFFER_SIZE 256 417 418 #define CONFIG_FSL_DEVICE_DISABLE 419 420 421 #ifdef CONFIG_LPUART 422 #define CONFIG_EXTRA_ENV_SETTINGS \ 423 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ 424 "initrd_high=0xffffffff\0" \ 425 "fdt_high=0xffffffff\0" 426 #else 427 #define CONFIG_EXTRA_ENV_SETTINGS \ 428 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 429 "initrd_high=0xffffffff\0" \ 430 "fdt_high=0xffffffff\0" 431 #endif 432 433 /* 434 * Miscellaneous configurable options 435 */ 436 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 437 #define CONFIG_AUTO_COMPLETE 438 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 439 #define CONFIG_SYS_PBSIZE \ 440 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 441 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 442 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 443 444 #define CONFIG_SYS_MEMTEST_START 0x80000000 445 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 446 447 #define CONFIG_SYS_LOAD_ADDR 0x82000000 448 449 #define CONFIG_LS102XA_STREAM_ID 450 451 /* 452 * Stack sizes 453 * The stack sizes are set up in start.S using the settings below 454 */ 455 #define CONFIG_STACKSIZE (30 * 1024) 456 457 #define CONFIG_SYS_INIT_SP_OFFSET \ 458 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 459 #define CONFIG_SYS_INIT_SP_ADDR \ 460 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 461 462 #ifdef CONFIG_SPL_BUILD 463 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 464 #else 465 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 466 #endif 467 468 #define CONFIG_SYS_QE_FW_ADDR 0x600c0000 469 470 /* 471 * Environment 472 */ 473 #define CONFIG_ENV_OVERWRITE 474 475 #if defined(CONFIG_SD_BOOT) 476 #define CONFIG_ENV_OFFSET 0x100000 477 #define CONFIG_ENV_IS_IN_MMC 478 #define CONFIG_SYS_MMC_ENV_DEV 0 479 #define CONFIG_ENV_SIZE 0x20000 480 #elif defined(CONFIG_QSPI_BOOT) 481 #define CONFIG_ENV_IS_IN_SPI_FLASH 482 #define CONFIG_ENV_SIZE 0x2000 483 #define CONFIG_ENV_OFFSET 0x100000 484 #define CONFIG_ENV_SECT_SIZE 0x10000 485 #else 486 #define CONFIG_ENV_IS_IN_FLASH 487 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 488 #define CONFIG_ENV_SIZE 0x20000 489 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 490 #endif 491 492 #define CONFIG_MISC_INIT_R 493 494 /* Hash command with SHA acceleration supported in hardware */ 495 #ifdef CONFIG_FSL_CAAM 496 #define CONFIG_CMD_HASH 497 #define CONFIG_SHA_HW_ACCEL 498 #endif 499 500 #include <asm/fsl_secure_boot.h> 501 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 502 503 #endif 504