xref: /openbmc/u-boot/include/configs/ls1021atwr.h (revision 4519668b)
1 /*
2  * Copyright 2014 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef __CONFIG_H
8 #define __CONFIG_H
9 
10 #define CONFIG_LS102XA
11 
12 #define CONFIG_ARMV7_PSCI
13 
14 #define CONFIG_SYS_GENERIC_BOARD
15 
16 #define CONFIG_DISPLAY_CPUINFO
17 #define CONFIG_DISPLAY_BOARDINFO
18 
19 #define CONFIG_SKIP_LOWLEVEL_INIT
20 #define CONFIG_BOARD_EARLY_INIT_F
21 #define CONFIG_DEEP_SLEEP
22 #ifdef CONFIG_DEEP_SLEEP
23 #define CONFIG_SILENT_CONSOLE
24 #endif
25 
26 /*
27  * Size of malloc() pool
28  */
29 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 16 * 1024 * 1024)
30 
31 #define CONFIG_SYS_INIT_RAM_ADDR	OCRAM_BASE_ADDR
32 #define CONFIG_SYS_INIT_RAM_SIZE	OCRAM_SIZE
33 
34 /*
35  * USB
36  */
37 
38 /*
39  * EHCI Support - disbaled by default as
40  * there is no signal coming out of soc on
41  * this board for this controller. However,
42  * the silicon still has this controller,
43  * and anyone can use this controller by
44  * taking signals out on their board.
45  */
46 
47 /*#define CONFIG_HAS_FSL_DR_USB*/
48 
49 #ifdef CONFIG_HAS_FSL_DR_USB
50 #define CONFIG_USB_EHCI
51 #define CONFIG_USB_EHCI_FSL
52 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
53 #endif
54 
55 /* XHCI Support - enabled by default */
56 #define CONFIG_HAS_FSL_XHCI_USB
57 
58 #ifdef CONFIG_HAS_FSL_XHCI_USB
59 #define CONFIG_USB_XHCI_FSL
60 #define CONFIG_USB_XHCI_DWC3
61 #define CONFIG_USB_XHCI
62 #define CONFIG_USB_MAX_CONTROLLER_COUNT        1
63 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS     2
64 #endif
65 
66 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
67 #define CONFIG_CMD_USB
68 #define CONFIG_USB_STORAGE
69 #define CONFIG_CMD_EXT2
70 #endif
71 
72 /*
73  * Generic Timer Definitions
74  */
75 #define GENERIC_TIMER_CLK		12500000
76 
77 #define CONFIG_SYS_CLK_FREQ		100000000
78 #define CONFIG_DDR_CLK_FREQ		100000000
79 
80 #define DDR_SDRAM_CFG			0x470c0008
81 #define DDR_CS0_BNDS			0x008000bf
82 #define DDR_CS0_CONFIG			0x80014302
83 #define DDR_TIMING_CFG_0		0x50550004
84 #define DDR_TIMING_CFG_1		0xbcb38c56
85 #define DDR_TIMING_CFG_2		0x0040d120
86 #define DDR_TIMING_CFG_3		0x010e1000
87 #define DDR_TIMING_CFG_4		0x00000001
88 #define DDR_TIMING_CFG_5		0x03401400
89 #define DDR_SDRAM_CFG_2			0x00401010
90 #define DDR_SDRAM_MODE			0x00061c60
91 #define DDR_SDRAM_MODE_2		0x00180000
92 #define DDR_SDRAM_INTERVAL		0x18600618
93 #define DDR_DDR_WRLVL_CNTL		0x8655f605
94 #define DDR_DDR_WRLVL_CNTL_2		0x05060607
95 #define DDR_DDR_WRLVL_CNTL_3		0x05050505
96 #define DDR_DDR_CDR1			0x80040000
97 #define DDR_DDR_CDR2			0x00000001
98 #define DDR_SDRAM_CLK_CNTL		0x02000000
99 #define DDR_DDR_ZQ_CNTL			0x89080600
100 #define DDR_CS0_CONFIG_2		0
101 #define DDR_SDRAM_CFG_MEM_EN		0x80000000
102 #define SDRAM_CFG2_D_INIT		0x00000010
103 #define DDR_CDR2_VREF_TRAIN_EN		0x00000080
104 #define SDRAM_CFG2_FRC_SR		0x80000000
105 #define SDRAM_CFG_BI			0x00000001
106 
107 #ifdef CONFIG_RAMBOOT_PBL
108 #define CONFIG_SYS_FSL_PBL_PBI	board/freescale/ls1021atwr/ls102xa_pbi.cfg
109 #endif
110 
111 #ifdef CONFIG_SD_BOOT
112 #define CONFIG_SYS_FSL_PBL_RCW	board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg
113 #define CONFIG_SPL_FRAMEWORK
114 #define CONFIG_SPL_LDSCRIPT	"arch/$(ARCH)/cpu/u-boot-spl.lds"
115 #define CONFIG_SPL_LIBCOMMON_SUPPORT
116 #define CONFIG_SPL_LIBGENERIC_SUPPORT
117 #define CONFIG_SPL_ENV_SUPPORT
118 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
119 #define CONFIG_SPL_I2C_SUPPORT
120 #define CONFIG_SPL_WATCHDOG_SUPPORT
121 #define CONFIG_SPL_SERIAL_SUPPORT
122 #define CONFIG_SPL_MMC_SUPPORT
123 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR		0xe8
124 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS		0x400
125 
126 #define CONFIG_SPL_TEXT_BASE		0x10000000
127 #define CONFIG_SPL_MAX_SIZE		0x1a000
128 #define CONFIG_SPL_STACK		0x1001d000
129 #define CONFIG_SPL_PAD_TO		0x1c000
130 #define CONFIG_SYS_TEXT_BASE		0x82000000
131 
132 #define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE + \
133 		CONFIG_SYS_MONITOR_LEN)
134 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
135 #define CONFIG_SPL_BSS_START_ADDR	0x80100000
136 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000
137 #define CONFIG_SYS_MONITOR_LEN		0x80000
138 #endif
139 
140 #ifdef CONFIG_QSPI_BOOT
141 #define CONFIG_SYS_TEXT_BASE		0x40010000
142 #define CONFIG_SYS_NO_FLASH
143 #endif
144 
145 #ifndef CONFIG_SYS_TEXT_BASE
146 #define CONFIG_SYS_TEXT_BASE		0x60100000
147 #endif
148 
149 #define CONFIG_NR_DRAM_BANKS		1
150 #define PHYS_SDRAM			0x80000000
151 #define PHYS_SDRAM_SIZE			(1u * 1024 * 1024 * 1024)
152 
153 #define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
154 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
155 
156 #define CONFIG_SYS_HAS_SERDES
157 
158 #define CONFIG_FSL_CAAM			/* Enable CAAM */
159 
160 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
161 	!defined(CONFIG_QSPI_BOOT)
162 #define CONFIG_U_QE
163 #endif
164 
165 /*
166  * IFC Definitions
167  */
168 #ifndef CONFIG_QSPI_BOOT
169 #define CONFIG_FSL_IFC
170 #define CONFIG_SYS_FLASH_BASE		0x60000000
171 #define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
172 
173 #define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
174 #define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
175 				CSPR_PORT_SIZE_16 | \
176 				CSPR_MSEL_NOR | \
177 				CSPR_V)
178 #define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128 * 1024 * 1024)
179 
180 /* NOR Flash Timing Params */
181 #define CONFIG_SYS_NOR_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
182 					CSOR_NOR_TRHZ_80)
183 #define CONFIG_SYS_NOR_FTIM0		(FTIM0_NOR_TACSE(0x4) | \
184 					FTIM0_NOR_TEADC(0x5) | \
185 					FTIM0_NOR_TAVDS(0x0) | \
186 					FTIM0_NOR_TEAHC(0x5))
187 #define CONFIG_SYS_NOR_FTIM1		(FTIM1_NOR_TACO(0x35) | \
188 					FTIM1_NOR_TRAD_NOR(0x1A) | \
189 					FTIM1_NOR_TSEQRAD_NOR(0x13))
190 #define CONFIG_SYS_NOR_FTIM2		(FTIM2_NOR_TCS(0x4) | \
191 					FTIM2_NOR_TCH(0x4) | \
192 					FTIM2_NOR_TWP(0x1c) | \
193 					FTIM2_NOR_TWPH(0x0e))
194 #define CONFIG_SYS_NOR_FTIM3		0
195 
196 #define CONFIG_FLASH_CFI_DRIVER
197 #define CONFIG_SYS_FLASH_CFI
198 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
199 #define CONFIG_SYS_FLASH_QUIET_TEST
200 #define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
201 
202 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
203 #define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
204 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
205 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
206 
207 #define CONFIG_SYS_FLASH_EMPTY_INFO
208 #define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE_PHYS }
209 
210 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
211 #define CONFIG_SYS_WRITE_SWAPPED_DATA
212 #endif
213 
214 /* CPLD */
215 
216 #define CONFIG_SYS_CPLD_BASE	0x7fb00000
217 #define CPLD_BASE_PHYS		CONFIG_SYS_CPLD_BASE
218 
219 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
220 #define CONFIG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
221 					CSPR_PORT_SIZE_8 | \
222 					CSPR_MSEL_GPCM | \
223 					CSPR_V)
224 #define CONFIG_SYS_FPGA_AMASK		IFC_AMASK(64 * 1024)
225 #define CONFIG_SYS_FPGA_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
226 					CSOR_NOR_NOR_MODE_AVD_NOR | \
227 					CSOR_NOR_TRHZ_80)
228 
229 /* CPLD Timing parameters for IFC GPCM */
230 #define CONFIG_SYS_FPGA_FTIM0		(FTIM0_GPCM_TACSE(0xf) | \
231 					FTIM0_GPCM_TEADC(0xf) | \
232 					FTIM0_GPCM_TEAHC(0xf))
233 #define CONFIG_SYS_FPGA_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
234 					FTIM1_GPCM_TRAD(0x3f))
235 #define CONFIG_SYS_FPGA_FTIM2		(FTIM2_GPCM_TCS(0xf) | \
236 					FTIM2_GPCM_TCH(0xf) | \
237 					FTIM2_GPCM_TWP(0xff))
238 #define CONFIG_SYS_FPGA_FTIM3           0x0
239 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
240 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
241 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
242 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
243 #define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
244 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
245 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
246 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
247 #define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_FPGA_CSPR_EXT
248 #define CONFIG_SYS_CSPR1		CONFIG_SYS_FPGA_CSPR
249 #define CONFIG_SYS_AMASK1		CONFIG_SYS_FPGA_AMASK
250 #define CONFIG_SYS_CSOR1		CONFIG_SYS_FPGA_CSOR
251 #define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_FPGA_FTIM0
252 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_FPGA_FTIM1
253 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_FPGA_FTIM2
254 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_FPGA_FTIM3
255 
256 /*
257  * Serial Port
258  */
259 #ifdef CONFIG_LPUART
260 #define CONFIG_FSL_LPUART
261 #define CONFIG_LPUART_32B_REG
262 #else
263 #define CONFIG_CONS_INDEX		1
264 #define CONFIG_SYS_NS16550
265 #define CONFIG_SYS_NS16550_SERIAL
266 #define CONFIG_SYS_NS16550_REG_SIZE	1
267 #define CONFIG_SYS_NS16550_CLK		get_serial_clock()
268 #endif
269 
270 #define CONFIG_BAUDRATE			115200
271 
272 /*
273  * I2C
274  */
275 #define CONFIG_CMD_I2C
276 #define CONFIG_SYS_I2C
277 #define CONFIG_SYS_I2C_MXC
278 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
279 
280 /* EEPROM */
281 #ifndef CONFIG_SD_BOOT
282 #define CONFIG_ID_EEPROM
283 #define CONFIG_SYS_I2C_EEPROM_NXID
284 #define CONFIG_SYS_EEPROM_BUS_NUM		1
285 #define CONFIG_SYS_I2C_EEPROM_ADDR		0x53
286 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
287 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
288 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
289 #endif
290 
291 /*
292  * MMC
293  */
294 #define CONFIG_MMC
295 #define CONFIG_CMD_MMC
296 #define CONFIG_FSL_ESDHC
297 #define CONFIG_GENERIC_MMC
298 
299 #define CONFIG_CMD_FAT
300 #define CONFIG_DOS_PARTITION
301 
302 /* SPI */
303 #ifdef CONFIG_QSPI_BOOT
304 /* QSPI */
305 #define CONFIG_FSL_QSPI
306 #define QSPI0_AMBA_BASE			0x40000000
307 #define FSL_QSPI_FLASH_SIZE		(1 << 24)
308 #define FSL_QSPI_FLASH_NUM		2
309 #define CONFIG_SPI_FLASH_STMICRO
310 
311 /* DM SPI */
312 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
313 #define CONFIG_CMD_SF
314 #define CONFIG_DM_SPI_FLASH
315 #endif
316 #endif
317 
318 /*
319  * Video
320  */
321 #define CONFIG_FSL_DCU_FB
322 
323 #ifdef CONFIG_FSL_DCU_FB
324 #define CONFIG_VIDEO
325 #define CONFIG_CMD_BMP
326 #define CONFIG_CFB_CONSOLE
327 #define CONFIG_VGA_AS_SINGLE_DEVICE
328 #define CONFIG_VIDEO_LOGO
329 #define CONFIG_VIDEO_BMP_LOGO
330 
331 #define CONFIG_FSL_DCU_SII9022A
332 #define CONFIG_SYS_I2C_DVI_BUS_NUM	1
333 #define CONFIG_SYS_I2C_DVI_ADDR		0x39
334 #endif
335 
336 /*
337  * eTSEC
338  */
339 #define CONFIG_TSEC_ENET
340 
341 #ifdef CONFIG_TSEC_ENET
342 #define CONFIG_MII
343 #define CONFIG_MII_DEFAULT_TSEC		1
344 #define CONFIG_TSEC1			1
345 #define CONFIG_TSEC1_NAME		"eTSEC1"
346 #define CONFIG_TSEC2			1
347 #define CONFIG_TSEC2_NAME		"eTSEC2"
348 #define CONFIG_TSEC3			1
349 #define CONFIG_TSEC3_NAME		"eTSEC3"
350 
351 #define TSEC1_PHY_ADDR			2
352 #define TSEC2_PHY_ADDR			0
353 #define TSEC3_PHY_ADDR			1
354 
355 #define TSEC1_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
356 #define TSEC2_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
357 #define TSEC3_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
358 
359 #define TSEC1_PHYIDX			0
360 #define TSEC2_PHYIDX			0
361 #define TSEC3_PHYIDX			0
362 
363 #define CONFIG_ETHPRIME			"eTSEC1"
364 
365 #define CONFIG_PHY_GIGE
366 #define CONFIG_PHYLIB
367 #define CONFIG_PHY_ATHEROS
368 
369 #define CONFIG_HAS_ETH0
370 #define CONFIG_HAS_ETH1
371 #define CONFIG_HAS_ETH2
372 #endif
373 
374 /* PCIe */
375 #define CONFIG_PCI		/* Enable PCI/PCIE */
376 #define CONFIG_PCIE1		/* PCIE controler 1 */
377 #define CONFIG_PCIE2		/* PCIE controler 2 */
378 #define CONFIG_PCIE_LAYERSCAPE	/* Use common FSL Layerscape PCIe code */
379 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
380 
381 #define CONFIG_SYS_PCI_64BIT
382 
383 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF	0x00000000
384 #define CONFIG_SYS_PCIE_CFG0_SIZE	0x00001000	/* 4k */
385 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF	0x00001000
386 #define CONFIG_SYS_PCIE_CFG1_SIZE	0x00001000	/* 4k */
387 
388 #define CONFIG_SYS_PCIE_IO_BUS		0x00000000
389 #define CONFIG_SYS_PCIE_IO_PHYS_OFF	0x00010000
390 #define CONFIG_SYS_PCIE_IO_SIZE		0x00010000	/* 64k */
391 
392 #define CONFIG_SYS_PCIE_MEM_BUS		0x08000000
393 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF	0x04000000
394 #define CONFIG_SYS_PCIE_MEM_SIZE	0x08000000	/* 128M */
395 
396 #ifdef CONFIG_PCI
397 #define CONFIG_PCI_PNP
398 #define CONFIG_PCI_SCAN_SHOW
399 #define CONFIG_CMD_PCI
400 #endif
401 
402 #define CONFIG_CMD_PING
403 #define CONFIG_CMD_DHCP
404 #define CONFIG_CMD_MII
405 
406 #define CONFIG_CMDLINE_TAG
407 #define CONFIG_CMDLINE_EDITING
408 
409 #define CONFIG_ARMV7_NONSEC
410 #define CONFIG_ARMV7_VIRT
411 #define CONFIG_PEN_ADDR_BIG_ENDIAN
412 #define CONFIG_LS102XA_NS_ACCESS
413 #define CONFIG_SMP_PEN_ADDR		0x01ee0200
414 #define CONFIG_TIMER_CLK_FREQ		12500000
415 
416 #define CONFIG_HWCONFIG
417 #define HWCONFIG_BUFFER_SIZE		128
418 
419 #define CONFIG_BOOTDELAY		3
420 
421 #ifdef CONFIG_LPUART
422 #define CONFIG_EXTRA_ENV_SETTINGS       \
423 	"bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
424 	"initrd_high=0xcfffffff\0"      \
425 	"fdt_high=0xcfffffff\0"
426 #else
427 #define CONFIG_EXTRA_ENV_SETTINGS	\
428 	"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
429 	"initrd_high=0xcfffffff\0"      \
430 	"fdt_high=0xcfffffff\0"
431 #endif
432 
433 /*
434  * Miscellaneous configurable options
435  */
436 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
437 #define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
438 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
439 #define CONFIG_AUTO_COMPLETE
440 #define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
441 #define CONFIG_SYS_PBSIZE		\
442 		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
443 #define CONFIG_SYS_MAXARGS		16	/* max number of command args */
444 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
445 
446 #define CONFIG_CMD_GREPENV
447 #define CONFIG_CMD_MEMINFO
448 #define CONFIG_CMD_MEMTEST
449 #define CONFIG_SYS_MEMTEST_START	0x80000000
450 #define CONFIG_SYS_MEMTEST_END		0x9fffffff
451 
452 #define CONFIG_SYS_LOAD_ADDR		0x82000000
453 
454 #define CONFIG_LS102XA_STREAM_ID
455 
456 /*
457  * Stack sizes
458  * The stack sizes are set up in start.S using the settings below
459  */
460 #define CONFIG_STACKSIZE		(30 * 1024)
461 
462 #define CONFIG_SYS_INIT_SP_OFFSET \
463 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
464 #define CONFIG_SYS_INIT_SP_ADDR \
465 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
466 
467 #ifdef CONFIG_SPL_BUILD
468 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
469 #else
470 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
471 #endif
472 
473 #define CONFIG_SYS_QE_FW_ADDR     0x67f40000
474 
475 /*
476  * Environment
477  */
478 #define CONFIG_ENV_OVERWRITE
479 
480 #if defined(CONFIG_SD_BOOT)
481 #define CONFIG_ENV_OFFSET		0x100000
482 #define CONFIG_ENV_IS_IN_MMC
483 #define CONFIG_SYS_MMC_ENV_DEV		0
484 #define CONFIG_ENV_SIZE			0x20000
485 #elif defined(CONFIG_QSPI_BOOT)
486 #define CONFIG_ENV_IS_IN_SPI_FLASH
487 #define CONFIG_ENV_SIZE			0x2000
488 #define CONFIG_ENV_OFFSET		0x100000
489 #define CONFIG_ENV_SECT_SIZE		0x10000
490 #else
491 #define CONFIG_ENV_IS_IN_FLASH
492 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
493 #define CONFIG_ENV_SIZE			0x20000
494 #define CONFIG_ENV_SECT_SIZE		0x20000 /* 128K (one sector) */
495 #endif
496 
497 #define CONFIG_OF_LIBFDT
498 #define CONFIG_OF_BOARD_SETUP
499 #define CONFIG_CMD_BOOTZ
500 
501 #define CONFIG_MISC_INIT_R
502 
503 /* Hash command with SHA acceleration supported in hardware */
504 #define CONFIG_CMD_HASH
505 #define CONFIG_SHA_HW_ACCEL
506 
507 #ifdef CONFIG_SECURE_BOOT
508 #define CONFIG_CMD_BLOB
509 #include <asm/fsl_secure_boot.h>
510 #endif
511 
512 #endif
513