1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_LS102XA 11 12 #define CONFIG_ARMV7_PSCI_1_0 13 14 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 15 16 #define CONFIG_SYS_FSL_CLK 17 18 #define CONFIG_DISPLAY_CPUINFO 19 #define CONFIG_DISPLAY_BOARDINFO 20 21 #define CONFIG_SKIP_LOWLEVEL_INIT 22 #define CONFIG_BOARD_EARLY_INIT_F 23 #define CONFIG_DEEP_SLEEP 24 #ifdef CONFIG_DEEP_SLEEP 25 #define CONFIG_SILENT_CONSOLE 26 #endif 27 28 /* 29 * Size of malloc() pool 30 */ 31 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 32 33 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 34 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 35 36 /* 37 * USB 38 */ 39 40 /* 41 * EHCI Support - disbaled by default as 42 * there is no signal coming out of soc on 43 * this board for this controller. However, 44 * the silicon still has this controller, 45 * and anyone can use this controller by 46 * taking signals out on their board. 47 */ 48 49 /*#define CONFIG_HAS_FSL_DR_USB*/ 50 51 #ifdef CONFIG_HAS_FSL_DR_USB 52 #define CONFIG_USB_EHCI 53 #define CONFIG_USB_EHCI_FSL 54 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 55 #endif 56 57 /* XHCI Support - enabled by default */ 58 #define CONFIG_HAS_FSL_XHCI_USB 59 60 #ifdef CONFIG_HAS_FSL_XHCI_USB 61 #define CONFIG_USB_XHCI_FSL 62 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 63 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 64 #endif 65 66 /* 67 * Generic Timer Definitions 68 */ 69 #define GENERIC_TIMER_CLK 12500000 70 71 #define CONFIG_SYS_CLK_FREQ 100000000 72 #define CONFIG_DDR_CLK_FREQ 100000000 73 74 #define DDR_SDRAM_CFG 0x470c0008 75 #define DDR_CS0_BNDS 0x008000bf 76 #define DDR_CS0_CONFIG 0x80014302 77 #define DDR_TIMING_CFG_0 0x50550004 78 #define DDR_TIMING_CFG_1 0xbcb38c56 79 #define DDR_TIMING_CFG_2 0x0040d120 80 #define DDR_TIMING_CFG_3 0x010e1000 81 #define DDR_TIMING_CFG_4 0x00000001 82 #define DDR_TIMING_CFG_5 0x03401400 83 #define DDR_SDRAM_CFG_2 0x00401010 84 #define DDR_SDRAM_MODE 0x00061c60 85 #define DDR_SDRAM_MODE_2 0x00180000 86 #define DDR_SDRAM_INTERVAL 0x18600618 87 #define DDR_DDR_WRLVL_CNTL 0x8655f605 88 #define DDR_DDR_WRLVL_CNTL_2 0x05060607 89 #define DDR_DDR_WRLVL_CNTL_3 0x05050505 90 #define DDR_DDR_CDR1 0x80040000 91 #define DDR_DDR_CDR2 0x00000001 92 #define DDR_SDRAM_CLK_CNTL 0x02000000 93 #define DDR_DDR_ZQ_CNTL 0x89080600 94 #define DDR_CS0_CONFIG_2 0 95 #define DDR_SDRAM_CFG_MEM_EN 0x80000000 96 #define SDRAM_CFG2_D_INIT 0x00000010 97 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080 98 #define SDRAM_CFG2_FRC_SR 0x80000000 99 #define SDRAM_CFG_BI 0x00000001 100 101 #ifdef CONFIG_RAMBOOT_PBL 102 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg 103 #endif 104 105 #ifdef CONFIG_SD_BOOT 106 #ifdef CONFIG_SD_BOOT_QSPI 107 #define CONFIG_SYS_FSL_PBL_RCW \ 108 board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg 109 #else 110 #define CONFIG_SYS_FSL_PBL_RCW \ 111 board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg 112 #endif 113 #define CONFIG_SPL_FRAMEWORK 114 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 115 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 116 117 #ifdef CONFIG_SECURE_BOOT 118 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 119 /* 120 * HDR would be appended at end of image and copied to DDR along 121 * with U-Boot image. 122 */ 123 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS (0x400 + \ 124 (CONFIG_U_BOOT_HDR_SIZE / 512) 125 #else 126 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 127 #endif /* ifdef CONFIG_SECURE_BOOT */ 128 129 #define CONFIG_SPL_TEXT_BASE 0x10000000 130 #define CONFIG_SPL_MAX_SIZE 0x1a000 131 #define CONFIG_SPL_STACK 0x1001d000 132 #define CONFIG_SPL_PAD_TO 0x1c000 133 #define CONFIG_SYS_TEXT_BASE 0x82000000 134 135 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 136 CONFIG_SYS_MONITOR_LEN) 137 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 138 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 139 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 140 141 #ifdef CONFIG_U_BOOT_HDR_SIZE 142 /* 143 * HDR would be appended at end of image and copied to DDR along 144 * with U-Boot image. Here u-boot max. size is 512K. So if binary 145 * size increases then increase this size in case of secure boot as 146 * it uses raw u-boot image instead of fit image. 147 */ 148 #define CONFIG_SYS_MONITOR_LEN (0x80000 + CONFIG_U_BOOT_HDR_SIZE) 149 #else 150 #define CONFIG_SYS_MONITOR_LEN 0x80000 151 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ 152 #endif 153 154 #ifdef CONFIG_QSPI_BOOT 155 #define CONFIG_SYS_TEXT_BASE 0x40010000 156 #endif 157 158 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 159 #define CONFIG_SYS_NO_FLASH 160 #endif 161 162 #ifndef CONFIG_SYS_TEXT_BASE 163 #define CONFIG_SYS_TEXT_BASE 0x60100000 164 #endif 165 166 #define CONFIG_NR_DRAM_BANKS 1 167 #define PHYS_SDRAM 0x80000000 168 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) 169 170 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 171 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 172 173 #define CONFIG_SYS_HAS_SERDES 174 175 #define CONFIG_FSL_CAAM /* Enable CAAM */ 176 177 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ 178 !defined(CONFIG_QSPI_BOOT) 179 #define CONFIG_U_QE 180 #endif 181 182 /* 183 * IFC Definitions 184 */ 185 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 186 #define CONFIG_FSL_IFC 187 #define CONFIG_SYS_FLASH_BASE 0x60000000 188 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 189 190 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 191 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 192 CSPR_PORT_SIZE_16 | \ 193 CSPR_MSEL_NOR | \ 194 CSPR_V) 195 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 196 197 /* NOR Flash Timing Params */ 198 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 199 CSOR_NOR_TRHZ_80) 200 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 201 FTIM0_NOR_TEADC(0x5) | \ 202 FTIM0_NOR_TAVDS(0x0) | \ 203 FTIM0_NOR_TEAHC(0x5)) 204 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 205 FTIM1_NOR_TRAD_NOR(0x1A) | \ 206 FTIM1_NOR_TSEQRAD_NOR(0x13)) 207 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 208 FTIM2_NOR_TCH(0x4) | \ 209 FTIM2_NOR_TWP(0x1c) | \ 210 FTIM2_NOR_TWPH(0x0e)) 211 #define CONFIG_SYS_NOR_FTIM3 0 212 213 #define CONFIG_FLASH_CFI_DRIVER 214 #define CONFIG_SYS_FLASH_CFI 215 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 216 #define CONFIG_SYS_FLASH_QUIET_TEST 217 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 218 219 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 220 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 221 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 222 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 223 224 #define CONFIG_SYS_FLASH_EMPTY_INFO 225 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 226 227 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 228 #define CONFIG_SYS_WRITE_SWAPPED_DATA 229 #endif 230 231 /* CPLD */ 232 233 #define CONFIG_SYS_CPLD_BASE 0x7fb00000 234 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 235 236 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 237 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ 238 CSPR_PORT_SIZE_8 | \ 239 CSPR_MSEL_GPCM | \ 240 CSPR_V) 241 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 242 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 243 CSOR_NOR_NOR_MODE_AVD_NOR | \ 244 CSOR_NOR_TRHZ_80) 245 246 /* CPLD Timing parameters for IFC GPCM */ 247 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ 248 FTIM0_GPCM_TEADC(0xf) | \ 249 FTIM0_GPCM_TEAHC(0xf)) 250 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 251 FTIM1_GPCM_TRAD(0x3f)) 252 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 253 FTIM2_GPCM_TCH(0xf) | \ 254 FTIM2_GPCM_TWP(0xff)) 255 #define CONFIG_SYS_FPGA_FTIM3 0x0 256 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 257 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 258 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 259 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 260 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 261 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 262 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 263 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 264 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT 265 #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR 266 #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK 267 #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR 268 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0 269 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1 270 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2 271 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3 272 273 /* 274 * Serial Port 275 */ 276 #ifdef CONFIG_LPUART 277 #define CONFIG_LPUART_32B_REG 278 #else 279 #define CONFIG_CONS_INDEX 1 280 #define CONFIG_SYS_NS16550_SERIAL 281 #ifndef CONFIG_DM_SERIAL 282 #define CONFIG_SYS_NS16550_REG_SIZE 1 283 #endif 284 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 285 #endif 286 287 #define CONFIG_BAUDRATE 115200 288 289 /* 290 * I2C 291 */ 292 #define CONFIG_SYS_I2C 293 #define CONFIG_SYS_I2C_MXC 294 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 295 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 296 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 297 298 /* EEPROM */ 299 #define CONFIG_ID_EEPROM 300 #define CONFIG_SYS_I2C_EEPROM_NXID 301 #define CONFIG_SYS_EEPROM_BUS_NUM 1 302 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 303 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 304 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 305 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 306 307 /* 308 * MMC 309 */ 310 #define CONFIG_MMC 311 #define CONFIG_FSL_ESDHC 312 #define CONFIG_GENERIC_MMC 313 314 #define CONFIG_DOS_PARTITION 315 316 /* SPI */ 317 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 318 /* QSPI */ 319 #define QSPI0_AMBA_BASE 0x40000000 320 #define FSL_QSPI_FLASH_SIZE (1 << 24) 321 #define FSL_QSPI_FLASH_NUM 2 322 323 /* DSPI */ 324 #endif 325 326 /* DM SPI */ 327 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 328 #define CONFIG_DM_SPI_FLASH 329 #endif 330 331 /* 332 * Video 333 */ 334 #define CONFIG_FSL_DCU_FB 335 336 #ifdef CONFIG_FSL_DCU_FB 337 #define CONFIG_VIDEO 338 #define CONFIG_CMD_BMP 339 #define CONFIG_CFB_CONSOLE 340 #define CONFIG_VGA_AS_SINGLE_DEVICE 341 #define CONFIG_VIDEO_LOGO 342 #define CONFIG_VIDEO_BMP_LOGO 343 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 344 345 #define CONFIG_FSL_DCU_SII9022A 346 #define CONFIG_SYS_I2C_DVI_BUS_NUM 1 347 #define CONFIG_SYS_I2C_DVI_ADDR 0x39 348 #endif 349 350 /* 351 * eTSEC 352 */ 353 #define CONFIG_TSEC_ENET 354 355 #ifdef CONFIG_TSEC_ENET 356 #define CONFIG_MII 357 #define CONFIG_MII_DEFAULT_TSEC 1 358 #define CONFIG_TSEC1 1 359 #define CONFIG_TSEC1_NAME "eTSEC1" 360 #define CONFIG_TSEC2 1 361 #define CONFIG_TSEC2_NAME "eTSEC2" 362 #define CONFIG_TSEC3 1 363 #define CONFIG_TSEC3_NAME "eTSEC3" 364 365 #define TSEC1_PHY_ADDR 2 366 #define TSEC2_PHY_ADDR 0 367 #define TSEC3_PHY_ADDR 1 368 369 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 370 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 371 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 372 373 #define TSEC1_PHYIDX 0 374 #define TSEC2_PHYIDX 0 375 #define TSEC3_PHYIDX 0 376 377 #define CONFIG_ETHPRIME "eTSEC1" 378 379 #define CONFIG_PHY_GIGE 380 #define CONFIG_PHYLIB 381 #define CONFIG_PHY_ATHEROS 382 383 #define CONFIG_HAS_ETH0 384 #define CONFIG_HAS_ETH1 385 #define CONFIG_HAS_ETH2 386 #endif 387 388 /* PCIe */ 389 #define CONFIG_PCI /* Enable PCI/PCIE */ 390 #define CONFIG_PCIE1 /* PCIE controller 1 */ 391 #define CONFIG_PCIE2 /* PCIE controller 2 */ 392 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 393 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" 394 395 #define CONFIG_SYS_PCI_64BIT 396 397 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 398 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ 399 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 400 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ 401 402 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 403 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 404 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ 405 406 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 407 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 408 #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ 409 410 #ifdef CONFIG_PCI 411 #define CONFIG_PCI_PNP 412 #define CONFIG_PCI_SCAN_SHOW 413 #define CONFIG_CMD_PCI 414 #endif 415 416 #define CONFIG_CMDLINE_TAG 417 #define CONFIG_CMDLINE_EDITING 418 419 #define CONFIG_ARMV7_NONSEC 420 #define CONFIG_ARMV7_VIRT 421 #define CONFIG_PEN_ADDR_BIG_ENDIAN 422 #define CONFIG_LAYERSCAPE_NS_ACCESS 423 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 424 #define CONFIG_TIMER_CLK_FREQ 12500000 425 426 #define CONFIG_HWCONFIG 427 #define HWCONFIG_BUFFER_SIZE 256 428 429 #define CONFIG_FSL_DEVICE_DISABLE 430 431 432 #ifdef CONFIG_LPUART 433 #define CONFIG_EXTRA_ENV_SETTINGS \ 434 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ 435 "initrd_high=0xffffffff\0" \ 436 "fdt_high=0xffffffff\0" 437 #else 438 #define CONFIG_EXTRA_ENV_SETTINGS \ 439 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 440 "initrd_high=0xffffffff\0" \ 441 "fdt_high=0xffffffff\0" 442 #endif 443 444 /* 445 * Miscellaneous configurable options 446 */ 447 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 448 #define CONFIG_AUTO_COMPLETE 449 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 450 #define CONFIG_SYS_PBSIZE \ 451 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 452 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 453 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 454 455 #define CONFIG_SYS_MEMTEST_START 0x80000000 456 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 457 458 #define CONFIG_SYS_LOAD_ADDR 0x82000000 459 460 #define CONFIG_LS102XA_STREAM_ID 461 462 /* 463 * Stack sizes 464 * The stack sizes are set up in start.S using the settings below 465 */ 466 #define CONFIG_STACKSIZE (30 * 1024) 467 468 #define CONFIG_SYS_INIT_SP_OFFSET \ 469 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 470 #define CONFIG_SYS_INIT_SP_ADDR \ 471 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 472 473 #ifdef CONFIG_SPL_BUILD 474 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 475 #else 476 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 477 #endif 478 479 #define CONFIG_SYS_QE_FW_ADDR 0x600c0000 480 481 /* 482 * Environment 483 */ 484 #define CONFIG_ENV_OVERWRITE 485 486 #if defined(CONFIG_SD_BOOT) 487 #define CONFIG_ENV_OFFSET 0x100000 488 #define CONFIG_ENV_IS_IN_MMC 489 #define CONFIG_SYS_MMC_ENV_DEV 0 490 #define CONFIG_ENV_SIZE 0x20000 491 #elif defined(CONFIG_QSPI_BOOT) 492 #define CONFIG_ENV_IS_IN_SPI_FLASH 493 #define CONFIG_ENV_SIZE 0x2000 494 #define CONFIG_ENV_OFFSET 0x100000 495 #define CONFIG_ENV_SECT_SIZE 0x10000 496 #else 497 #define CONFIG_ENV_IS_IN_FLASH 498 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 499 #define CONFIG_ENV_SIZE 0x20000 500 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 501 #endif 502 503 #define CONFIG_MISC_INIT_R 504 505 /* Hash command with SHA acceleration supported in hardware */ 506 #ifdef CONFIG_FSL_CAAM 507 #define CONFIG_CMD_HASH 508 #define CONFIG_SHA_HW_ACCEL 509 #endif 510 511 #include <asm/fsl_secure_boot.h> 512 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 513 514 #endif 515