1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __CONFIG_H 7 #define __CONFIG_H 8 9 #define CONFIG_ARMV7_PSCI_1_0 10 11 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 12 13 #define CONFIG_SYS_FSL_CLK 14 15 #define CONFIG_SKIP_LOWLEVEL_INIT 16 #define CONFIG_DEEP_SLEEP 17 18 /* 19 * Size of malloc() pool 20 */ 21 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 22 23 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 24 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 25 26 #define CONFIG_SYS_CLK_FREQ 100000000 27 #define CONFIG_DDR_CLK_FREQ 100000000 28 29 #define DDR_SDRAM_CFG 0x470c0008 30 #define DDR_CS0_BNDS 0x008000bf 31 #define DDR_CS0_CONFIG 0x80014302 32 #define DDR_TIMING_CFG_0 0x50550004 33 #define DDR_TIMING_CFG_1 0xbcb38c56 34 #define DDR_TIMING_CFG_2 0x0040d120 35 #define DDR_TIMING_CFG_3 0x010e1000 36 #define DDR_TIMING_CFG_4 0x00000001 37 #define DDR_TIMING_CFG_5 0x03401400 38 #define DDR_SDRAM_CFG_2 0x00401010 39 #define DDR_SDRAM_MODE 0x00061c60 40 #define DDR_SDRAM_MODE_2 0x00180000 41 #define DDR_SDRAM_INTERVAL 0x18600618 42 #define DDR_DDR_WRLVL_CNTL 0x8655f605 43 #define DDR_DDR_WRLVL_CNTL_2 0x05060607 44 #define DDR_DDR_WRLVL_CNTL_3 0x05050505 45 #define DDR_DDR_CDR1 0x80040000 46 #define DDR_DDR_CDR2 0x00000001 47 #define DDR_SDRAM_CLK_CNTL 0x02000000 48 #define DDR_DDR_ZQ_CNTL 0x89080600 49 #define DDR_CS0_CONFIG_2 0 50 #define DDR_SDRAM_CFG_MEM_EN 0x80000000 51 #define SDRAM_CFG2_D_INIT 0x00000010 52 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080 53 #define SDRAM_CFG2_FRC_SR 0x80000000 54 #define SDRAM_CFG_BI 0x00000001 55 56 #ifdef CONFIG_RAMBOOT_PBL 57 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg 58 #endif 59 60 #ifdef CONFIG_SD_BOOT 61 #ifdef CONFIG_SD_BOOT_QSPI 62 #define CONFIG_SYS_FSL_PBL_RCW \ 63 board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg 64 #else 65 #define CONFIG_SYS_FSL_PBL_RCW \ 66 board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg 67 #endif 68 69 #ifdef CONFIG_SECURE_BOOT 70 /* 71 * HDR would be appended at end of image and copied to DDR along 72 * with U-Boot image. 73 */ 74 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 75 #endif /* ifdef CONFIG_SECURE_BOOT */ 76 77 #define CONFIG_SPL_TEXT_BASE 0x10000000 78 #define CONFIG_SPL_MAX_SIZE 0x1a000 79 #define CONFIG_SPL_STACK 0x1001d000 80 #define CONFIG_SPL_PAD_TO 0x1c000 81 82 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 83 CONFIG_SYS_MONITOR_LEN) 84 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 85 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 86 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 87 88 #ifdef CONFIG_U_BOOT_HDR_SIZE 89 /* 90 * HDR would be appended at end of image and copied to DDR along 91 * with U-Boot image. Here u-boot max. size is 512K. So if binary 92 * size increases then increase this size in case of secure boot as 93 * it uses raw u-boot image instead of fit image. 94 */ 95 #define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) 96 #else 97 #define CONFIG_SYS_MONITOR_LEN 0x100000 98 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ 99 #endif 100 101 #define PHYS_SDRAM 0x80000000 102 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) 103 104 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 105 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 106 107 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ 108 !defined(CONFIG_QSPI_BOOT) 109 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 110 #endif 111 112 /* 113 * IFC Definitions 114 */ 115 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 116 #define CONFIG_FSL_IFC 117 #define CONFIG_SYS_FLASH_BASE 0x60000000 118 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 119 120 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 121 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 122 CSPR_PORT_SIZE_16 | \ 123 CSPR_MSEL_NOR | \ 124 CSPR_V) 125 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 126 127 /* NOR Flash Timing Params */ 128 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 129 CSOR_NOR_TRHZ_80) 130 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 131 FTIM0_NOR_TEADC(0x5) | \ 132 FTIM0_NOR_TAVDS(0x0) | \ 133 FTIM0_NOR_TEAHC(0x5)) 134 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 135 FTIM1_NOR_TRAD_NOR(0x1A) | \ 136 FTIM1_NOR_TSEQRAD_NOR(0x13)) 137 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 138 FTIM2_NOR_TCH(0x4) | \ 139 FTIM2_NOR_TWP(0x1c) | \ 140 FTIM2_NOR_TWPH(0x0e)) 141 #define CONFIG_SYS_NOR_FTIM3 0 142 143 #define CONFIG_FLASH_CFI_DRIVER 144 #define CONFIG_SYS_FLASH_CFI 145 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 146 #define CONFIG_SYS_FLASH_QUIET_TEST 147 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 148 149 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 150 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 151 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 152 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 153 154 #define CONFIG_SYS_FLASH_EMPTY_INFO 155 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 156 157 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 158 #define CONFIG_SYS_WRITE_SWAPPED_DATA 159 #endif 160 161 /* CPLD */ 162 163 #define CONFIG_SYS_CPLD_BASE 0x7fb00000 164 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 165 166 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 167 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ 168 CSPR_PORT_SIZE_8 | \ 169 CSPR_MSEL_GPCM | \ 170 CSPR_V) 171 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 172 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 173 CSOR_NOR_NOR_MODE_AVD_NOR | \ 174 CSOR_NOR_TRHZ_80) 175 176 /* CPLD Timing parameters for IFC GPCM */ 177 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ 178 FTIM0_GPCM_TEADC(0xf) | \ 179 FTIM0_GPCM_TEAHC(0xf)) 180 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 181 FTIM1_GPCM_TRAD(0x3f)) 182 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 183 FTIM2_GPCM_TCH(0xf) | \ 184 FTIM2_GPCM_TWP(0xff)) 185 #define CONFIG_SYS_FPGA_FTIM3 0x0 186 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 187 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 188 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 189 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 190 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 191 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 192 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 193 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 194 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT 195 #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR 196 #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK 197 #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR 198 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0 199 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1 200 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2 201 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3 202 203 /* 204 * Serial Port 205 */ 206 #ifdef CONFIG_LPUART 207 #define CONFIG_LPUART_32B_REG 208 #else 209 #define CONFIG_SYS_NS16550_SERIAL 210 #ifndef CONFIG_DM_SERIAL 211 #define CONFIG_SYS_NS16550_REG_SIZE 1 212 #endif 213 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 214 #endif 215 216 /* 217 * I2C 218 */ 219 #define CONFIG_SYS_I2C 220 #define CONFIG_SYS_I2C_MXC 221 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 222 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 223 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 224 225 /* EEPROM */ 226 #define CONFIG_ID_EEPROM 227 #define CONFIG_SYS_I2C_EEPROM_NXID 228 #define CONFIG_SYS_EEPROM_BUS_NUM 1 229 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 230 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 231 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 232 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 233 234 /* 235 * MMC 236 */ 237 238 /* SPI */ 239 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 240 /* QSPI */ 241 #define QSPI0_AMBA_BASE 0x40000000 242 #define FSL_QSPI_FLASH_SIZE (1 << 24) 243 #define FSL_QSPI_FLASH_NUM 2 244 245 /* DSPI */ 246 #endif 247 248 /* DM SPI */ 249 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 250 #define CONFIG_DM_SPI_FLASH 251 #endif 252 253 /* 254 * Video 255 */ 256 #ifdef CONFIG_VIDEO_FSL_DCU_FB 257 #define CONFIG_VIDEO_LOGO 258 #define CONFIG_VIDEO_BMP_LOGO 259 260 #define CONFIG_FSL_DCU_SII9022A 261 #define CONFIG_SYS_I2C_DVI_BUS_NUM 1 262 #define CONFIG_SYS_I2C_DVI_ADDR 0x39 263 #endif 264 265 /* 266 * eTSEC 267 */ 268 269 #ifdef CONFIG_TSEC_ENET 270 #define CONFIG_MII_DEFAULT_TSEC 1 271 #define CONFIG_TSEC1 1 272 #define CONFIG_TSEC1_NAME "eTSEC1" 273 #define CONFIG_TSEC2 1 274 #define CONFIG_TSEC2_NAME "eTSEC2" 275 #define CONFIG_TSEC3 1 276 #define CONFIG_TSEC3_NAME "eTSEC3" 277 278 #define TSEC1_PHY_ADDR 2 279 #define TSEC2_PHY_ADDR 0 280 #define TSEC3_PHY_ADDR 1 281 282 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 283 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 284 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 285 286 #define TSEC1_PHYIDX 0 287 #define TSEC2_PHYIDX 0 288 #define TSEC3_PHYIDX 0 289 290 #define CONFIG_ETHPRIME "eTSEC1" 291 292 #define CONFIG_PHY_ATHEROS 293 294 #define CONFIG_HAS_ETH0 295 #define CONFIG_HAS_ETH1 296 #define CONFIG_HAS_ETH2 297 #endif 298 299 /* PCIe */ 300 #define CONFIG_PCIE1 /* PCIE controller 1 */ 301 #define CONFIG_PCIE2 /* PCIE controller 2 */ 302 303 #ifdef CONFIG_PCI 304 #define CONFIG_PCI_SCAN_SHOW 305 #endif 306 307 #define CONFIG_CMDLINE_TAG 308 309 #define CONFIG_PEN_ADDR_BIG_ENDIAN 310 #define CONFIG_LAYERSCAPE_NS_ACCESS 311 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 312 #define COUNTER_FREQUENCY 12500000 313 314 #define CONFIG_HWCONFIG 315 #define HWCONFIG_BUFFER_SIZE 256 316 317 #define CONFIG_FSL_DEVICE_DISABLE 318 319 #define BOOT_TARGET_DEVICES(func) \ 320 func(MMC, mmc, 0) \ 321 func(USB, usb, 0) 322 #include <config_distro_bootcmd.h> 323 324 #ifdef CONFIG_LPUART 325 #define CONFIG_EXTRA_ENV_SETTINGS \ 326 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ 327 "initrd_high=0xffffffff\0" \ 328 "fdt_high=0xffffffff\0" \ 329 "fdt_addr=0x64f00000\0" \ 330 "kernel_addr=0x65000000\0" \ 331 "scriptaddr=0x80000000\0" \ 332 "scripthdraddr=0x80080000\0" \ 333 "fdtheader_addr_r=0x80100000\0" \ 334 "kernelheader_addr_r=0x80200000\0" \ 335 "kernel_addr_r=0x81000000\0" \ 336 "fdt_addr_r=0x90000000\0" \ 337 "ramdisk_addr_r=0xa0000000\0" \ 338 "load_addr=0xa0000000\0" \ 339 "kernel_size=0x2800000\0" \ 340 "kernel_addr_sd=0x8000\0" \ 341 "kernel_size_sd=0x14000\0" \ 342 BOOTENV \ 343 "boot_scripts=ls1021atwr_boot.scr\0" \ 344 "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \ 345 "scan_dev_for_boot_part=" \ 346 "part list ${devtype} ${devnum} devplist; " \ 347 "env exists devplist || setenv devplist 1; " \ 348 "for distro_bootpart in ${devplist}; do " \ 349 "if fstype ${devtype} " \ 350 "${devnum}:${distro_bootpart} " \ 351 "bootfstype; then " \ 352 "run scan_dev_for_boot; " \ 353 "fi; " \ 354 "done\0" \ 355 "scan_dev_for_boot=" \ 356 "echo Scanning ${devtype} " \ 357 "${devnum}:${distro_bootpart}...; " \ 358 "for prefix in ${boot_prefixes}; do " \ 359 "run scan_dev_for_scripts; " \ 360 "done;" \ 361 "\0" \ 362 "boot_a_script=" \ 363 "load ${devtype} ${devnum}:${distro_bootpart} " \ 364 "${scriptaddr} ${prefix}${script}; " \ 365 "env exists secureboot && load ${devtype} " \ 366 "${devnum}:${distro_bootpart} " \ 367 "${scripthdraddr} ${prefix}${boot_script_hdr} " \ 368 "&& esbc_validate ${scripthdraddr};" \ 369 "source ${scriptaddr}\0" \ 370 "installer=load mmc 0:2 $load_addr " \ 371 "/flex_installer_arm32.itb; " \ 372 "bootm $load_addr#ls1021atwr\0" \ 373 "qspi_bootcmd=echo Trying load from qspi..;" \ 374 "sf probe && sf read $load_addr " \ 375 "$kernel_addr $kernel_size && bootm $load_addr#$board\0" \ 376 "nor_bootcmd=echo Trying load from nor..;" \ 377 "cp.b $kernel_addr $load_addr " \ 378 "$kernel_size && bootm $load_addr#$board\0" 379 #else 380 #define CONFIG_EXTRA_ENV_SETTINGS \ 381 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 382 "initrd_high=0xffffffff\0" \ 383 "fdt_high=0xffffffff\0" \ 384 "fdt_addr=0x64f00000\0" \ 385 "kernel_addr=0x61000000\0" \ 386 "kernelheader_addr=0x60800000\0" \ 387 "scriptaddr=0x80000000\0" \ 388 "scripthdraddr=0x80080000\0" \ 389 "fdtheader_addr_r=0x80100000\0" \ 390 "kernelheader_addr_r=0x80200000\0" \ 391 "kernel_addr_r=0x81000000\0" \ 392 "kernelheader_size=0x40000\0" \ 393 "fdt_addr_r=0x90000000\0" \ 394 "ramdisk_addr_r=0xa0000000\0" \ 395 "load_addr=0xa0000000\0" \ 396 "kernel_size=0x2800000\0" \ 397 "kernel_addr_sd=0x8000\0" \ 398 "kernel_size_sd=0x14000\0" \ 399 "kernelhdr_addr_sd=0x4000\0" \ 400 "kernelhdr_size_sd=0x10\0" \ 401 BOOTENV \ 402 "boot_scripts=ls1021atwr_boot.scr\0" \ 403 "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \ 404 "scan_dev_for_boot_part=" \ 405 "part list ${devtype} ${devnum} devplist; " \ 406 "env exists devplist || setenv devplist 1; " \ 407 "for distro_bootpart in ${devplist}; do " \ 408 "if fstype ${devtype} " \ 409 "${devnum}:${distro_bootpart} " \ 410 "bootfstype; then " \ 411 "run scan_dev_for_boot; " \ 412 "fi; " \ 413 "done\0" \ 414 "scan_dev_for_boot=" \ 415 "echo Scanning ${devtype} " \ 416 "${devnum}:${distro_bootpart}...; " \ 417 "for prefix in ${boot_prefixes}; do " \ 418 "run scan_dev_for_scripts; " \ 419 "done;" \ 420 "\0" \ 421 "boot_a_script=" \ 422 "load ${devtype} ${devnum}:${distro_bootpart} " \ 423 "${scriptaddr} ${prefix}${script}; " \ 424 "env exists secureboot && load ${devtype} " \ 425 "${devnum}:${distro_bootpart} " \ 426 "${scripthdraddr} ${prefix}${boot_script_hdr} " \ 427 "&& esbc_validate ${scripthdraddr};" \ 428 "source ${scriptaddr}\0" \ 429 "qspi_bootcmd=echo Trying load from qspi..;" \ 430 "sf probe && sf read $load_addr " \ 431 "$kernel_addr $kernel_size; env exists secureboot " \ 432 "&& sf read $kernelheader_addr_r $kernelheader_addr " \ 433 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ 434 "bootm $load_addr#$board\0" \ 435 "nor_bootcmd=echo Trying load from nor..;" \ 436 "cp.b $kernel_addr $load_addr " \ 437 "$kernel_size; env exists secureboot " \ 438 "&& cp.b $kernelheader_addr $kernelheader_addr_r " \ 439 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ 440 "bootm $load_addr#$board\0" \ 441 "sd_bootcmd=echo Trying load from SD ..;" \ 442 "mmcinfo && mmc read $load_addr " \ 443 "$kernel_addr_sd $kernel_size_sd && " \ 444 "env exists secureboot && mmc read $kernelheader_addr_r " \ 445 "$kernelhdr_addr_sd $kernelhdr_size_sd " \ 446 " && esbc_validate ${kernelheader_addr_r};" \ 447 "bootm $load_addr#$board\0" 448 #endif 449 450 #undef CONFIG_BOOTCOMMAND 451 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 452 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd" \ 453 "env exists secureboot && esbc_halt" 454 #elif defined(CONFIG_SD_BOOT) 455 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ 456 "env exists secureboot && esbc_halt;" 457 #else 458 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd;" \ 459 "env exists secureboot && esbc_halt;" 460 #endif 461 462 /* 463 * Miscellaneous configurable options 464 */ 465 466 #define CONFIG_SYS_MEMTEST_START 0x80000000 467 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 468 469 #define CONFIG_SYS_LOAD_ADDR 0x82000000 470 471 #define CONFIG_LS102XA_STREAM_ID 472 473 #define CONFIG_SYS_INIT_SP_OFFSET \ 474 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 475 #define CONFIG_SYS_INIT_SP_ADDR \ 476 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 477 478 #ifdef CONFIG_SPL_BUILD 479 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 480 #else 481 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 482 #endif 483 484 #define CONFIG_SYS_QE_FW_ADDR 0x60940000 485 486 /* 487 * Environment 488 */ 489 #define CONFIG_ENV_OVERWRITE 490 491 #if defined(CONFIG_SD_BOOT) 492 #define CONFIG_ENV_OFFSET 0x300000 493 #define CONFIG_SYS_MMC_ENV_DEV 0 494 #define CONFIG_ENV_SIZE 0x20000 495 #elif defined(CONFIG_QSPI_BOOT) 496 #define CONFIG_ENV_SIZE 0x2000 497 #define CONFIG_ENV_OFFSET 0x300000 498 #define CONFIG_ENV_SECT_SIZE 0x10000 499 #else 500 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 501 #define CONFIG_ENV_SIZE 0x20000 502 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 503 #endif 504 505 #include <asm/fsl_secure_boot.h> 506 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 507 508 #endif 509