1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_LS102XA 11 12 #define CONFIG_ARMV7_PSCI 13 14 #define CONFIG_SYS_GENERIC_BOARD 15 16 #define CONFIG_DISPLAY_CPUINFO 17 #define CONFIG_DISPLAY_BOARDINFO 18 19 #define CONFIG_SKIP_LOWLEVEL_INIT 20 #define CONFIG_BOARD_EARLY_INIT_F 21 22 /* 23 * Size of malloc() pool 24 */ 25 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 26 27 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 28 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 29 30 /* 31 * USB 32 */ 33 34 /* 35 * EHCI Support - disbaled by default as 36 * there is no signal coming out of soc on 37 * this board for this controller. However, 38 * the silicon still has this controller, 39 * and anyone can use this controller by 40 * taking signals out on their board. 41 */ 42 43 /*#define CONFIG_HAS_FSL_DR_USB*/ 44 45 #ifdef CONFIG_HAS_FSL_DR_USB 46 #define CONFIG_USB_EHCI 47 #define CONFIG_USB_EHCI_FSL 48 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 49 #endif 50 51 /* XHCI Support - enabled by default */ 52 #define CONFIG_HAS_FSL_XHCI_USB 53 54 #ifdef CONFIG_HAS_FSL_XHCI_USB 55 #define CONFIG_USB_XHCI_FSL 56 #define CONFIG_USB_XHCI_DWC3 57 #define CONFIG_USB_XHCI 58 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 59 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 60 #endif 61 62 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB) 63 #define CONFIG_CMD_USB 64 #define CONFIG_USB_STORAGE 65 #define CONFIG_CMD_EXT2 66 #endif 67 68 /* 69 * Generic Timer Definitions 70 */ 71 #define GENERIC_TIMER_CLK 12500000 72 73 #define CONFIG_SYS_CLK_FREQ 100000000 74 #define CONFIG_DDR_CLK_FREQ 100000000 75 76 #define DDR_SDRAM_CFG 0x470c0008 77 #define DDR_CS0_BNDS 0x008000bf 78 #define DDR_CS0_CONFIG 0x80014302 79 #define DDR_TIMING_CFG_0 0x50550004 80 #define DDR_TIMING_CFG_1 0xbcb38c56 81 #define DDR_TIMING_CFG_2 0x0040d120 82 #define DDR_TIMING_CFG_3 0x010e1000 83 #define DDR_TIMING_CFG_4 0x00000001 84 #define DDR_TIMING_CFG_5 0x03401400 85 #define DDR_SDRAM_CFG_2 0x00401010 86 #define DDR_SDRAM_MODE 0x00061c60 87 #define DDR_SDRAM_MODE_2 0x00180000 88 #define DDR_SDRAM_INTERVAL 0x18600618 89 #define DDR_DDR_WRLVL_CNTL 0x8655f605 90 #define DDR_DDR_WRLVL_CNTL_2 0x05060607 91 #define DDR_DDR_WRLVL_CNTL_3 0x05050505 92 #define DDR_DDR_CDR1 0x80040000 93 #define DDR_DDR_CDR2 0x00000001 94 #define DDR_SDRAM_CLK_CNTL 0x02000000 95 #define DDR_DDR_ZQ_CNTL 0x89080600 96 #define DDR_CS0_CONFIG_2 0 97 #define DDR_SDRAM_CFG_MEM_EN 0x80000000 98 99 #ifdef CONFIG_RAMBOOT_PBL 100 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg 101 #endif 102 103 #ifdef CONFIG_SD_BOOT 104 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg 105 #define CONFIG_SPL_FRAMEWORK 106 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 107 #define CONFIG_SPL_LIBCOMMON_SUPPORT 108 #define CONFIG_SPL_LIBGENERIC_SUPPORT 109 #define CONFIG_SPL_ENV_SUPPORT 110 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 111 #define CONFIG_SPL_I2C_SUPPORT 112 #define CONFIG_SPL_WATCHDOG_SUPPORT 113 #define CONFIG_SPL_SERIAL_SUPPORT 114 #define CONFIG_SPL_MMC_SUPPORT 115 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 116 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 117 118 #define CONFIG_SPL_TEXT_BASE 0x10000000 119 #define CONFIG_SPL_MAX_SIZE 0x1a000 120 #define CONFIG_SPL_STACK 0x1001d000 121 #define CONFIG_SPL_PAD_TO 0x1c000 122 #define CONFIG_SYS_TEXT_BASE 0x82000000 123 124 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 125 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 126 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 127 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 128 #define CONFIG_SYS_MONITOR_LEN 0x80000 129 #endif 130 131 #ifdef CONFIG_QSPI_BOOT 132 #define CONFIG_SYS_TEXT_BASE 0x40010000 133 #define CONFIG_SYS_NO_FLASH 134 #endif 135 136 #ifndef CONFIG_SYS_TEXT_BASE 137 #define CONFIG_SYS_TEXT_BASE 0x60100000 138 #endif 139 140 #define CONFIG_NR_DRAM_BANKS 1 141 #define PHYS_SDRAM 0x80000000 142 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) 143 144 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 145 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 146 147 #define CONFIG_SYS_HAS_SERDES 148 149 #define CONFIG_FSL_CAAM /* Enable CAAM */ 150 151 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ 152 !defined(CONFIG_QSPI_BOOT) 153 #define CONFIG_U_QE 154 #endif 155 156 /* 157 * IFC Definitions 158 */ 159 #ifndef CONFIG_QSPI_BOOT 160 #define CONFIG_FSL_IFC 161 #define CONFIG_SYS_FLASH_BASE 0x60000000 162 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 163 164 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 165 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 166 CSPR_PORT_SIZE_16 | \ 167 CSPR_MSEL_NOR | \ 168 CSPR_V) 169 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 170 171 /* NOR Flash Timing Params */ 172 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 173 CSOR_NOR_TRHZ_80) 174 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 175 FTIM0_NOR_TEADC(0x5) | \ 176 FTIM0_NOR_TAVDS(0x0) | \ 177 FTIM0_NOR_TEAHC(0x5)) 178 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 179 FTIM1_NOR_TRAD_NOR(0x1A) | \ 180 FTIM1_NOR_TSEQRAD_NOR(0x13)) 181 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 182 FTIM2_NOR_TCH(0x4) | \ 183 FTIM2_NOR_TWP(0x1c) | \ 184 FTIM2_NOR_TWPH(0x0e)) 185 #define CONFIG_SYS_NOR_FTIM3 0 186 187 #define CONFIG_FLASH_CFI_DRIVER 188 #define CONFIG_SYS_FLASH_CFI 189 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 190 #define CONFIG_SYS_FLASH_QUIET_TEST 191 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 192 193 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 194 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 195 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 196 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 197 198 #define CONFIG_SYS_FLASH_EMPTY_INFO 199 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 200 201 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 202 #define CONFIG_SYS_WRITE_SWAPPED_DATA 203 #endif 204 205 /* CPLD */ 206 207 #define CONFIG_SYS_CPLD_BASE 0x7fb00000 208 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 209 210 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 211 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ 212 CSPR_PORT_SIZE_8 | \ 213 CSPR_MSEL_GPCM | \ 214 CSPR_V) 215 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 216 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 217 CSOR_NOR_NOR_MODE_AVD_NOR | \ 218 CSOR_NOR_TRHZ_80) 219 220 /* CPLD Timing parameters for IFC GPCM */ 221 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ 222 FTIM0_GPCM_TEADC(0xf) | \ 223 FTIM0_GPCM_TEAHC(0xf)) 224 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 225 FTIM1_GPCM_TRAD(0x3f)) 226 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 227 FTIM2_GPCM_TCH(0xf) | \ 228 FTIM2_GPCM_TWP(0xff)) 229 #define CONFIG_SYS_FPGA_FTIM3 0x0 230 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 231 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 232 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 233 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 234 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 235 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 236 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 237 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 238 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT 239 #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR 240 #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK 241 #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR 242 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0 243 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1 244 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2 245 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3 246 247 /* 248 * Serial Port 249 */ 250 #ifdef CONFIG_LPUART 251 #define CONFIG_FSL_LPUART 252 #define CONFIG_LPUART_32B_REG 253 #else 254 #define CONFIG_CONS_INDEX 1 255 #define CONFIG_SYS_NS16550 256 #define CONFIG_SYS_NS16550_SERIAL 257 #define CONFIG_SYS_NS16550_REG_SIZE 1 258 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 259 #endif 260 261 #define CONFIG_BAUDRATE 115200 262 263 /* 264 * I2C 265 */ 266 #define CONFIG_CMD_I2C 267 #define CONFIG_SYS_I2C 268 #define CONFIG_SYS_I2C_MXC 269 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 270 271 /* EEPROM */ 272 #ifndef CONFIG_SD_BOOT 273 #define CONFIG_ID_EEPROM 274 #define CONFIG_SYS_I2C_EEPROM_NXID 275 #define CONFIG_SYS_EEPROM_BUS_NUM 1 276 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 277 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 278 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 279 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 280 #endif 281 282 /* 283 * MMC 284 */ 285 #define CONFIG_MMC 286 #define CONFIG_CMD_MMC 287 #define CONFIG_FSL_ESDHC 288 #define CONFIG_GENERIC_MMC 289 290 #define CONFIG_CMD_FAT 291 #define CONFIG_DOS_PARTITION 292 293 /* SPI */ 294 #ifdef CONFIG_QSPI_BOOT 295 /* QSPI */ 296 #define CONFIG_FSL_QSPI 297 #define QSPI0_AMBA_BASE 0x40000000 298 #define FSL_QSPI_FLASH_SIZE (1 << 24) 299 #define FSL_QSPI_FLASH_NUM 2 300 #define CONFIG_SPI_FLASH_STMICRO 301 302 /* DM SPI */ 303 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 304 #define CONFIG_CMD_SF 305 #define CONFIG_DM_SPI_FLASH 306 #endif 307 #endif 308 309 /* 310 * Video 311 */ 312 #define CONFIG_FSL_DCU_FB 313 314 #ifdef CONFIG_FSL_DCU_FB 315 #define CONFIG_VIDEO 316 #define CONFIG_CMD_BMP 317 #define CONFIG_CFB_CONSOLE 318 #define CONFIG_VGA_AS_SINGLE_DEVICE 319 #define CONFIG_VIDEO_LOGO 320 #define CONFIG_VIDEO_BMP_LOGO 321 322 #define CONFIG_FSL_DCU_SII9022A 323 #define CONFIG_SYS_I2C_DVI_BUS_NUM 1 324 #define CONFIG_SYS_I2C_DVI_ADDR 0x39 325 #endif 326 327 /* 328 * eTSEC 329 */ 330 #define CONFIG_TSEC_ENET 331 332 #ifdef CONFIG_TSEC_ENET 333 #define CONFIG_MII 334 #define CONFIG_MII_DEFAULT_TSEC 1 335 #define CONFIG_TSEC1 1 336 #define CONFIG_TSEC1_NAME "eTSEC1" 337 #define CONFIG_TSEC2 1 338 #define CONFIG_TSEC2_NAME "eTSEC2" 339 #define CONFIG_TSEC3 1 340 #define CONFIG_TSEC3_NAME "eTSEC3" 341 342 #define TSEC1_PHY_ADDR 2 343 #define TSEC2_PHY_ADDR 0 344 #define TSEC3_PHY_ADDR 1 345 346 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 347 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 348 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 349 350 #define TSEC1_PHYIDX 0 351 #define TSEC2_PHYIDX 0 352 #define TSEC3_PHYIDX 0 353 354 #define CONFIG_ETHPRIME "eTSEC1" 355 356 #define CONFIG_PHY_GIGE 357 #define CONFIG_PHYLIB 358 #define CONFIG_PHY_ATHEROS 359 360 #define CONFIG_HAS_ETH0 361 #define CONFIG_HAS_ETH1 362 #define CONFIG_HAS_ETH2 363 #endif 364 365 /* PCIe */ 366 #define CONFIG_PCI /* Enable PCI/PCIE */ 367 #define CONFIG_PCIE1 /* PCIE controler 1 */ 368 #define CONFIG_PCIE2 /* PCIE controler 2 */ 369 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 370 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" 371 372 #define CONFIG_SYS_PCI_64BIT 373 374 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 375 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ 376 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 377 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ 378 379 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 380 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 381 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ 382 383 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 384 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 385 #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ 386 387 #ifdef CONFIG_PCI 388 #define CONFIG_PCI_PNP 389 #define CONFIG_E1000 390 #define CONFIG_PCI_SCAN_SHOW 391 #define CONFIG_CMD_PCI 392 #endif 393 394 #define CONFIG_CMD_PING 395 #define CONFIG_CMD_DHCP 396 #define CONFIG_CMD_MII 397 398 #define CONFIG_CMDLINE_TAG 399 #define CONFIG_CMDLINE_EDITING 400 401 #define CONFIG_ARMV7_NONSEC 402 #define CONFIG_ARMV7_VIRT 403 #define CONFIG_PEN_ADDR_BIG_ENDIAN 404 #define CONFIG_LS102XA_NS_ACCESS 405 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 406 #define CONFIG_TIMER_CLK_FREQ 12500000 407 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 408 409 #define CONFIG_HWCONFIG 410 #define HWCONFIG_BUFFER_SIZE 128 411 412 #define CONFIG_BOOTDELAY 3 413 414 #ifdef CONFIG_LPUART 415 #define CONFIG_EXTRA_ENV_SETTINGS \ 416 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ 417 "initrd_high=0xcfffffff\0" \ 418 "fdt_high=0xcfffffff\0" 419 #else 420 #define CONFIG_EXTRA_ENV_SETTINGS \ 421 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 422 "initrd_high=0xcfffffff\0" \ 423 "fdt_high=0xcfffffff\0" 424 #endif 425 426 /* 427 * Miscellaneous configurable options 428 */ 429 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 430 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 431 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 432 #define CONFIG_AUTO_COMPLETE 433 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 434 #define CONFIG_SYS_PBSIZE \ 435 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 436 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 437 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 438 439 #define CONFIG_CMD_GREPENV 440 #define CONFIG_CMD_MEMINFO 441 #define CONFIG_CMD_MEMTEST 442 #define CONFIG_SYS_MEMTEST_START 0x80000000 443 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 444 445 #define CONFIG_SYS_LOAD_ADDR 0x82000000 446 447 #define CONFIG_LS102XA_STREAM_ID 448 449 /* 450 * Stack sizes 451 * The stack sizes are set up in start.S using the settings below 452 */ 453 #define CONFIG_STACKSIZE (30 * 1024) 454 455 #define CONFIG_SYS_INIT_SP_OFFSET \ 456 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 457 #define CONFIG_SYS_INIT_SP_ADDR \ 458 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 459 460 #ifdef CONFIG_SPL_BUILD 461 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 462 #else 463 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 464 #endif 465 466 #define CONFIG_SYS_QE_FW_ADDR 0x67f40000 467 468 /* 469 * Environment 470 */ 471 #define CONFIG_ENV_OVERWRITE 472 473 #if defined(CONFIG_SD_BOOT) 474 #define CONFIG_ENV_OFFSET 0x100000 475 #define CONFIG_ENV_IS_IN_MMC 476 #define CONFIG_SYS_MMC_ENV_DEV 0 477 #define CONFIG_ENV_SIZE 0x20000 478 #elif defined(CONFIG_QSPI_BOOT) 479 #define CONFIG_ENV_IS_IN_SPI_FLASH 480 #define CONFIG_ENV_SIZE 0x2000 481 #define CONFIG_ENV_OFFSET 0x100000 482 #define CONFIG_ENV_SECT_SIZE 0x10000 483 #else 484 #define CONFIG_ENV_IS_IN_FLASH 485 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 486 #define CONFIG_ENV_SIZE 0x20000 487 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 488 #endif 489 490 #define CONFIG_OF_LIBFDT 491 #define CONFIG_OF_BOARD_SETUP 492 #define CONFIG_CMD_BOOTZ 493 494 #define CONFIG_MISC_INIT_R 495 496 /* Hash command with SHA acceleration supported in hardware */ 497 #define CONFIG_CMD_HASH 498 #define CONFIG_SHA_HW_ACCEL 499 500 #ifdef CONFIG_SECURE_BOOT 501 #define CONFIG_CMD_BLOB 502 #endif 503 504 #endif 505