1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __CONFIG_H 7 #define __CONFIG_H 8 9 #define CONFIG_ARMV7_PSCI_1_0 10 11 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 12 13 #define CONFIG_SYS_FSL_CLK 14 15 #define CONFIG_SKIP_LOWLEVEL_INIT 16 17 #define CONFIG_DEEP_SLEEP 18 19 /* 20 * Size of malloc() pool 21 */ 22 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 23 24 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 25 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 26 27 #ifndef __ASSEMBLY__ 28 unsigned long get_board_sys_clk(void); 29 unsigned long get_board_ddr_clk(void); 30 #endif 31 32 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 33 #define CONFIG_SYS_CLK_FREQ 100000000 34 #define CONFIG_DDR_CLK_FREQ 100000000 35 #define CONFIG_QIXIS_I2C_ACCESS 36 #else 37 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 38 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 39 #endif 40 41 #ifdef CONFIG_RAMBOOT_PBL 42 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg 43 #endif 44 45 #ifdef CONFIG_SD_BOOT 46 #ifdef CONFIG_SD_BOOT_QSPI 47 #define CONFIG_SYS_FSL_PBL_RCW \ 48 board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg 49 #else 50 #define CONFIG_SYS_FSL_PBL_RCW \ 51 board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg 52 #endif 53 54 #define CONFIG_SPL_TEXT_BASE 0x10000000 55 #define CONFIG_SPL_MAX_SIZE 0x1a000 56 #define CONFIG_SPL_STACK 0x1001d000 57 #define CONFIG_SPL_PAD_TO 0x1c000 58 59 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 60 CONFIG_SYS_MONITOR_LEN) 61 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 62 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 63 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 64 #define CONFIG_SYS_MONITOR_LEN 0xc0000 65 #endif 66 67 #ifdef CONFIG_NAND_BOOT 68 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg 69 70 #define CONFIG_SPL_TEXT_BASE 0x10000000 71 #define CONFIG_SPL_MAX_SIZE 0x1a000 72 #define CONFIG_SPL_STACK 0x1001d000 73 #define CONFIG_SPL_PAD_TO 0x1c000 74 75 #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10) 76 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 77 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 78 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 79 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 80 81 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 82 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 83 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 84 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 85 #define CONFIG_SYS_MONITOR_LEN 0x80000 86 #endif 87 88 #define CONFIG_DDR_SPD 89 #define SPD_EEPROM_ADDRESS 0x51 90 #define CONFIG_SYS_SPD_BUS_NUM 0 91 92 #ifndef CONFIG_SYS_FSL_DDR4 93 #define CONFIG_SYS_DDR_RAW_TIMING 94 #endif 95 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 96 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 97 98 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 99 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 100 101 #define CONFIG_DDR_ECC 102 #ifdef CONFIG_DDR_ECC 103 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 104 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 105 #endif 106 107 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ 108 !defined(CONFIG_QSPI_BOOT) 109 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 110 #endif 111 112 /* 113 * IFC Definitions 114 */ 115 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 116 #define CONFIG_FSL_IFC 117 #define CONFIG_SYS_FLASH_BASE 0x60000000 118 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 119 120 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 121 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 122 CSPR_PORT_SIZE_16 | \ 123 CSPR_MSEL_NOR | \ 124 CSPR_V) 125 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 126 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 127 + 0x8000000) | \ 128 CSPR_PORT_SIZE_16 | \ 129 CSPR_MSEL_NOR | \ 130 CSPR_V) 131 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 132 133 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 134 CSOR_NOR_TRHZ_80) 135 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 136 FTIM0_NOR_TEADC(0x5) | \ 137 FTIM0_NOR_TEAHC(0x5)) 138 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 139 FTIM1_NOR_TRAD_NOR(0x1a) | \ 140 FTIM1_NOR_TSEQRAD_NOR(0x13)) 141 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 142 FTIM2_NOR_TCH(0x4) | \ 143 FTIM2_NOR_TWPH(0xe) | \ 144 FTIM2_NOR_TWP(0x1c)) 145 #define CONFIG_SYS_NOR_FTIM3 0 146 147 #define CONFIG_SYS_FLASH_QUIET_TEST 148 #define CONFIG_FLASH_SHOW_PROGRESS 45 149 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 150 #define CONFIG_SYS_WRITE_SWAPPED_DATA 151 152 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 153 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 154 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 155 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 156 157 #define CONFIG_SYS_FLASH_EMPTY_INFO 158 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 159 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 160 161 /* 162 * NAND Flash Definitions 163 */ 164 #define CONFIG_NAND_FSL_IFC 165 166 #define CONFIG_SYS_NAND_BASE 0x7e800000 167 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 168 169 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 170 171 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 172 | CSPR_PORT_SIZE_8 \ 173 | CSPR_MSEL_NAND \ 174 | CSPR_V) 175 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 176 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 177 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 178 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 179 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 180 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 181 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 182 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 183 184 #define CONFIG_SYS_NAND_ONFI_DETECTION 185 186 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 187 FTIM0_NAND_TWP(0x18) | \ 188 FTIM0_NAND_TWCHT(0x7) | \ 189 FTIM0_NAND_TWH(0xa)) 190 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 191 FTIM1_NAND_TWBE(0x39) | \ 192 FTIM1_NAND_TRR(0xe) | \ 193 FTIM1_NAND_TRP(0x18)) 194 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 195 FTIM2_NAND_TREH(0xa) | \ 196 FTIM2_NAND_TWHRE(0x1e)) 197 #define CONFIG_SYS_NAND_FTIM3 0x0 198 199 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 200 #define CONFIG_SYS_MAX_NAND_DEVICE 1 201 202 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 203 #endif 204 205 /* 206 * QIXIS Definitions 207 */ 208 #define CONFIG_FSL_QIXIS 209 210 #ifdef CONFIG_FSL_QIXIS 211 #define QIXIS_BASE 0x7fb00000 212 #define QIXIS_BASE_PHYS QIXIS_BASE 213 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 214 #define QIXIS_LBMAP_SWITCH 6 215 #define QIXIS_LBMAP_MASK 0x0f 216 #define QIXIS_LBMAP_SHIFT 0 217 #define QIXIS_LBMAP_DFLTBANK 0x00 218 #define QIXIS_LBMAP_ALTBANK 0x04 219 #define QIXIS_PWR_CTL 0x21 220 #define QIXIS_PWR_CTL_POWEROFF 0x80 221 #define QIXIS_RST_CTL_RESET 0x44 222 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 223 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 224 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 225 #define QIXIS_CTL_SYS 0x5 226 #define QIXIS_CTL_SYS_EVTSW_MASK 0x0c 227 #define QIXIS_CTL_SYS_EVTSW_IRQ 0x04 228 #define QIXIS_RST_FORCE_3 0x45 229 #define QIXIS_RST_FORCE_3_PCIESLOT1 0x80 230 #define QIXIS_PWR_CTL2 0x21 231 #define QIXIS_PWR_CTL2_PCTL 0x2 232 233 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 234 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 235 CSPR_PORT_SIZE_8 | \ 236 CSPR_MSEL_GPCM | \ 237 CSPR_V) 238 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 239 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 240 CSOR_NOR_NOR_MODE_AVD_NOR | \ 241 CSOR_NOR_TRHZ_80) 242 243 /* 244 * QIXIS Timing parameters for IFC GPCM 245 */ 246 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \ 247 FTIM0_GPCM_TEADC(0xe) | \ 248 FTIM0_GPCM_TEAHC(0xe)) 249 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \ 250 FTIM1_GPCM_TRAD(0x1f)) 251 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \ 252 FTIM2_GPCM_TCH(0xe) | \ 253 FTIM2_GPCM_TWP(0xf0)) 254 #define CONFIG_SYS_FPGA_FTIM3 0x0 255 #endif 256 257 #if defined(CONFIG_NAND_BOOT) 258 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 259 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 260 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 261 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 262 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 263 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 264 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 265 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 266 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 267 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 268 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 269 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 270 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 271 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 272 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 273 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 274 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 275 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 276 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 277 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 278 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 279 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 280 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 281 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 282 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 283 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 284 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 285 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 286 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 287 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 288 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 289 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 290 #else 291 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 292 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 293 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 294 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 295 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 296 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 297 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 298 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 299 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 300 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 301 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 302 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 303 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 304 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 305 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 306 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 307 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 308 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 309 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 310 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 311 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 312 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 313 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 314 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 315 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 316 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 317 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 318 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 319 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 320 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 321 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 322 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 323 #endif 324 325 /* 326 * Serial Port 327 */ 328 #ifdef CONFIG_LPUART 329 #define CONFIG_LPUART_32B_REG 330 #else 331 #define CONFIG_SYS_NS16550_SERIAL 332 #ifndef CONFIG_DM_SERIAL 333 #define CONFIG_SYS_NS16550_REG_SIZE 1 334 #endif 335 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 336 #endif 337 338 /* 339 * I2C 340 */ 341 #define CONFIG_SYS_I2C 342 #define CONFIG_SYS_I2C_MXC 343 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 344 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 345 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 346 347 /* EEPROM */ 348 #define CONFIG_ID_EEPROM 349 #define CONFIG_SYS_I2C_EEPROM_NXID 350 #define CONFIG_SYS_EEPROM_BUS_NUM 0 351 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 352 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 353 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 354 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 355 356 /* 357 * I2C bus multiplexer 358 */ 359 #define I2C_MUX_PCA_ADDR_PRI 0x77 360 #define I2C_MUX_CH_DEFAULT 0x8 361 #define I2C_MUX_CH_CH7301 0xC 362 363 /* 364 * MMC 365 */ 366 367 /* SPI */ 368 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 369 /* QSPI */ 370 #define QSPI0_AMBA_BASE 0x40000000 371 #define FSL_QSPI_FLASH_SIZE (1 << 24) 372 #define FSL_QSPI_FLASH_NUM 2 373 374 /* DSPI */ 375 376 /* DM SPI */ 377 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 378 #define CONFIG_DM_SPI_FLASH 379 #define CONFIG_SPI_FLASH_DATAFLASH 380 #endif 381 #endif 382 383 /* 384 * Video 385 */ 386 #ifdef CONFIG_VIDEO_FSL_DCU_FB 387 #define CONFIG_VIDEO_LOGO 388 #define CONFIG_VIDEO_BMP_LOGO 389 390 #define CONFIG_FSL_DIU_CH7301 391 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0 392 #define CONFIG_SYS_I2C_QIXIS_ADDR 0x66 393 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 394 #endif 395 396 /* 397 * eTSEC 398 */ 399 400 #ifdef CONFIG_TSEC_ENET 401 #define CONFIG_MII_DEFAULT_TSEC 3 402 #define CONFIG_TSEC1 1 403 #define CONFIG_TSEC1_NAME "eTSEC1" 404 #define CONFIG_TSEC2 1 405 #define CONFIG_TSEC2_NAME "eTSEC2" 406 #define CONFIG_TSEC3 1 407 #define CONFIG_TSEC3_NAME "eTSEC3" 408 409 #define TSEC1_PHY_ADDR 1 410 #define TSEC2_PHY_ADDR 2 411 #define TSEC3_PHY_ADDR 3 412 413 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 414 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 415 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 416 417 #define TSEC1_PHYIDX 0 418 #define TSEC2_PHYIDX 0 419 #define TSEC3_PHYIDX 0 420 421 #define CONFIG_ETHPRIME "eTSEC1" 422 423 #define CONFIG_PHY_REALTEK 424 425 #define CONFIG_HAS_ETH0 426 #define CONFIG_HAS_ETH1 427 #define CONFIG_HAS_ETH2 428 429 #define CONFIG_FSL_SGMII_RISER 1 430 #define SGMII_RISER_PHY_OFFSET 0x1b 431 432 #ifdef CONFIG_FSL_SGMII_RISER 433 #define CONFIG_SYS_TBIPA_VALUE 8 434 #endif 435 436 #endif 437 438 /* PCIe */ 439 #define CONFIG_PCIE1 /* PCIE controller 1 */ 440 #define CONFIG_PCIE2 /* PCIE controller 2 */ 441 442 #ifdef CONFIG_PCI 443 #define CONFIG_PCI_SCAN_SHOW 444 #endif 445 446 #define CONFIG_CMDLINE_TAG 447 448 #define CONFIG_PEN_ADDR_BIG_ENDIAN 449 #define CONFIG_LAYERSCAPE_NS_ACCESS 450 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 451 #define COUNTER_FREQUENCY 12500000 452 453 #define CONFIG_HWCONFIG 454 #define HWCONFIG_BUFFER_SIZE 256 455 456 #define CONFIG_FSL_DEVICE_DISABLE 457 458 459 #define CONFIG_SYS_QE_FW_ADDR 0x60940000 460 461 #ifdef CONFIG_LPUART 462 #define CONFIG_EXTRA_ENV_SETTINGS \ 463 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ 464 "fdt_high=0xffffffff\0" \ 465 "initrd_high=0xffffffff\0" \ 466 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 467 #else 468 #define CONFIG_EXTRA_ENV_SETTINGS \ 469 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 470 "fdt_high=0xffffffff\0" \ 471 "initrd_high=0xffffffff\0" \ 472 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 473 #endif 474 475 /* 476 * Miscellaneous configurable options 477 */ 478 479 #define CONFIG_SYS_MEMTEST_START 0x80000000 480 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 481 482 #define CONFIG_SYS_LOAD_ADDR 0x82000000 483 484 #define CONFIG_LS102XA_STREAM_ID 485 486 #define CONFIG_SYS_INIT_SP_OFFSET \ 487 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 488 #define CONFIG_SYS_INIT_SP_ADDR \ 489 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 490 491 #ifdef CONFIG_SPL_BUILD 492 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 493 #else 494 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 495 #endif 496 497 /* 498 * Environment 499 */ 500 #define CONFIG_ENV_OVERWRITE 501 502 #if defined(CONFIG_SD_BOOT) 503 #define CONFIG_ENV_OFFSET 0x300000 504 #define CONFIG_SYS_MMC_ENV_DEV 0 505 #define CONFIG_ENV_SIZE 0x2000 506 #elif defined(CONFIG_QSPI_BOOT) 507 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 508 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ 509 #define CONFIG_ENV_SECT_SIZE 0x10000 510 #elif defined(CONFIG_NAND_BOOT) 511 #define CONFIG_ENV_SIZE 0x2000 512 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 513 #else 514 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 515 #define CONFIG_ENV_SIZE 0x2000 516 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 517 #endif 518 519 #include <asm/fsl_secure_boot.h> 520 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 521 522 #endif 523