1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_LS102XA 11 12 #define CONFIG_ARMV7_PSCI 13 14 #define CONFIG_SYS_FSL_CLK 15 16 #define CONFIG_DISPLAY_CPUINFO 17 #define CONFIG_DISPLAY_BOARDINFO 18 19 #define CONFIG_SKIP_LOWLEVEL_INIT 20 #define CONFIG_BOARD_EARLY_INIT_F 21 22 #define CONFIG_DEEP_SLEEP 23 #if defined(CONFIG_DEEP_SLEEP) 24 #define CONFIG_SILENT_CONSOLE 25 #endif 26 27 /* 28 * Size of malloc() pool 29 */ 30 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 31 32 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 33 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 34 35 /* 36 * Generic Timer Definitions 37 */ 38 #define GENERIC_TIMER_CLK 12500000 39 40 #ifndef __ASSEMBLY__ 41 unsigned long get_board_sys_clk(void); 42 unsigned long get_board_ddr_clk(void); 43 #endif 44 45 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 46 #define CONFIG_SYS_CLK_FREQ 100000000 47 #define CONFIG_DDR_CLK_FREQ 100000000 48 #define CONFIG_QIXIS_I2C_ACCESS 49 #else 50 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 51 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 52 #endif 53 54 #ifdef CONFIG_RAMBOOT_PBL 55 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg 56 #endif 57 58 #ifdef CONFIG_SD_BOOT 59 #ifdef CONFIG_SD_BOOT_QSPI 60 #define CONFIG_SYS_FSL_PBL_RCW \ 61 board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg 62 #else 63 #define CONFIG_SYS_FSL_PBL_RCW \ 64 board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg 65 #endif 66 #define CONFIG_SPL_FRAMEWORK 67 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 68 #define CONFIG_SPL_LIBCOMMON_SUPPORT 69 #define CONFIG_SPL_LIBGENERIC_SUPPORT 70 #define CONFIG_SPL_ENV_SUPPORT 71 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 72 #define CONFIG_SPL_I2C_SUPPORT 73 #define CONFIG_SPL_WATCHDOG_SUPPORT 74 #define CONFIG_SPL_SERIAL_SUPPORT 75 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 76 #define CONFIG_SPL_MMC_SUPPORT 77 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 78 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x600 79 80 #define CONFIG_SPL_TEXT_BASE 0x10000000 81 #define CONFIG_SPL_MAX_SIZE 0x1a000 82 #define CONFIG_SPL_STACK 0x1001d000 83 #define CONFIG_SPL_PAD_TO 0x1c000 84 #define CONFIG_SYS_TEXT_BASE 0x82000000 85 86 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 87 CONFIG_SYS_MONITOR_LEN) 88 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 89 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 90 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 91 #define CONFIG_SYS_MONITOR_LEN 0xc0000 92 #endif 93 94 #ifdef CONFIG_QSPI_BOOT 95 #define CONFIG_SYS_TEXT_BASE 0x40010000 96 #endif 97 98 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 99 #define CONFIG_SYS_NO_FLASH 100 #endif 101 102 #ifdef CONFIG_NAND_BOOT 103 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg 104 #define CONFIG_SPL_FRAMEWORK 105 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 106 #define CONFIG_SPL_LIBCOMMON_SUPPORT 107 #define CONFIG_SPL_LIBGENERIC_SUPPORT 108 #define CONFIG_SPL_ENV_SUPPORT 109 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 110 #define CONFIG_SPL_I2C_SUPPORT 111 #define CONFIG_SPL_WATCHDOG_SUPPORT 112 #define CONFIG_SPL_SERIAL_SUPPORT 113 #define CONFIG_SPL_NAND_SUPPORT 114 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 115 116 #define CONFIG_SPL_TEXT_BASE 0x10000000 117 #define CONFIG_SPL_MAX_SIZE 0x1a000 118 #define CONFIG_SPL_STACK 0x1001d000 119 #define CONFIG_SPL_PAD_TO 0x1c000 120 #define CONFIG_SYS_TEXT_BASE 0x82000000 121 122 #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10) 123 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 124 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 125 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 126 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 127 128 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 129 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 130 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 131 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 132 #define CONFIG_SYS_MONITOR_LEN 0x80000 133 #endif 134 135 #ifndef CONFIG_SYS_TEXT_BASE 136 #define CONFIG_SYS_TEXT_BASE 0x60100000 137 #endif 138 139 #define CONFIG_NR_DRAM_BANKS 1 140 141 #define CONFIG_DDR_SPD 142 #define SPD_EEPROM_ADDRESS 0x51 143 #define CONFIG_SYS_SPD_BUS_NUM 0 144 145 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 146 #ifndef CONFIG_SYS_FSL_DDR4 147 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ 148 #define CONFIG_SYS_DDR_RAW_TIMING 149 #endif 150 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 151 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 152 153 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 154 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 155 156 #define CONFIG_DDR_ECC 157 #ifdef CONFIG_DDR_ECC 158 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 159 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 160 #endif 161 162 #define CONFIG_SYS_HAS_SERDES 163 164 #define CONFIG_FSL_CAAM /* Enable CAAM */ 165 166 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ 167 !defined(CONFIG_QSPI_BOOT) 168 #define CONFIG_U_QE 169 #endif 170 171 /* 172 * IFC Definitions 173 */ 174 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 175 #define CONFIG_FSL_IFC 176 #define CONFIG_SYS_FLASH_BASE 0x60000000 177 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 178 179 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 180 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 181 CSPR_PORT_SIZE_16 | \ 182 CSPR_MSEL_NOR | \ 183 CSPR_V) 184 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 185 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 186 + 0x8000000) | \ 187 CSPR_PORT_SIZE_16 | \ 188 CSPR_MSEL_NOR | \ 189 CSPR_V) 190 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 191 192 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 193 CSOR_NOR_TRHZ_80) 194 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 195 FTIM0_NOR_TEADC(0x5) | \ 196 FTIM0_NOR_TEAHC(0x5)) 197 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 198 FTIM1_NOR_TRAD_NOR(0x1a) | \ 199 FTIM1_NOR_TSEQRAD_NOR(0x13)) 200 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 201 FTIM2_NOR_TCH(0x4) | \ 202 FTIM2_NOR_TWPH(0xe) | \ 203 FTIM2_NOR_TWP(0x1c)) 204 #define CONFIG_SYS_NOR_FTIM3 0 205 206 #define CONFIG_FLASH_CFI_DRIVER 207 #define CONFIG_SYS_FLASH_CFI 208 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 209 #define CONFIG_SYS_FLASH_QUIET_TEST 210 #define CONFIG_FLASH_SHOW_PROGRESS 45 211 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 212 #define CONFIG_SYS_WRITE_SWAPPED_DATA 213 214 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 215 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 216 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 217 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 218 219 #define CONFIG_SYS_FLASH_EMPTY_INFO 220 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 221 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 222 223 /* 224 * NAND Flash Definitions 225 */ 226 #define CONFIG_NAND_FSL_IFC 227 228 #define CONFIG_SYS_NAND_BASE 0x7e800000 229 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 230 231 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 232 233 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 234 | CSPR_PORT_SIZE_8 \ 235 | CSPR_MSEL_NAND \ 236 | CSPR_V) 237 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 238 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 239 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 240 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 241 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 242 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 243 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 244 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 245 246 #define CONFIG_SYS_NAND_ONFI_DETECTION 247 248 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 249 FTIM0_NAND_TWP(0x18) | \ 250 FTIM0_NAND_TWCHT(0x7) | \ 251 FTIM0_NAND_TWH(0xa)) 252 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 253 FTIM1_NAND_TWBE(0x39) | \ 254 FTIM1_NAND_TRR(0xe) | \ 255 FTIM1_NAND_TRP(0x18)) 256 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 257 FTIM2_NAND_TREH(0xa) | \ 258 FTIM2_NAND_TWHRE(0x1e)) 259 #define CONFIG_SYS_NAND_FTIM3 0x0 260 261 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 262 #define CONFIG_SYS_MAX_NAND_DEVICE 1 263 #define CONFIG_CMD_NAND 264 265 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 266 #endif 267 268 /* 269 * QIXIS Definitions 270 */ 271 #define CONFIG_FSL_QIXIS 272 273 #ifdef CONFIG_FSL_QIXIS 274 #define QIXIS_BASE 0x7fb00000 275 #define QIXIS_BASE_PHYS QIXIS_BASE 276 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 277 #define QIXIS_LBMAP_SWITCH 6 278 #define QIXIS_LBMAP_MASK 0x0f 279 #define QIXIS_LBMAP_SHIFT 0 280 #define QIXIS_LBMAP_DFLTBANK 0x00 281 #define QIXIS_LBMAP_ALTBANK 0x04 282 #define QIXIS_RST_CTL_RESET 0x44 283 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 284 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 285 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 286 287 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 288 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 289 CSPR_PORT_SIZE_8 | \ 290 CSPR_MSEL_GPCM | \ 291 CSPR_V) 292 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 293 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 294 CSOR_NOR_NOR_MODE_AVD_NOR | \ 295 CSOR_NOR_TRHZ_80) 296 297 /* 298 * QIXIS Timing parameters for IFC GPCM 299 */ 300 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \ 301 FTIM0_GPCM_TEADC(0xe) | \ 302 FTIM0_GPCM_TEAHC(0xe)) 303 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \ 304 FTIM1_GPCM_TRAD(0x1f)) 305 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \ 306 FTIM2_GPCM_TCH(0xe) | \ 307 FTIM2_GPCM_TWP(0xf0)) 308 #define CONFIG_SYS_FPGA_FTIM3 0x0 309 #endif 310 311 #if defined(CONFIG_NAND_BOOT) 312 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 313 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 314 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 315 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 316 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 317 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 318 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 319 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 320 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 321 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 322 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 323 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 324 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 325 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 326 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 327 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 328 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 329 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 330 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 331 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 332 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 333 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 334 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 335 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 336 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 337 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 338 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 339 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 340 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 341 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 342 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 343 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 344 #else 345 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 346 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 347 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 348 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 349 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 350 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 351 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 352 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 353 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 354 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 355 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 356 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 357 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 358 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 359 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 360 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 361 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 362 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 363 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 364 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 365 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 366 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 367 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 368 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 369 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 370 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 371 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 372 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 373 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 374 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 375 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 376 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 377 #endif 378 379 /* 380 * Serial Port 381 */ 382 #ifdef CONFIG_LPUART 383 #define CONFIG_LPUART_32B_REG 384 #else 385 #define CONFIG_CONS_INDEX 1 386 #define CONFIG_SYS_NS16550_SERIAL 387 #ifndef CONFIG_DM_SERIAL 388 #define CONFIG_SYS_NS16550_REG_SIZE 1 389 #endif 390 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 391 #endif 392 393 #define CONFIG_BAUDRATE 115200 394 395 /* 396 * I2C 397 */ 398 #define CONFIG_SYS_I2C 399 #define CONFIG_SYS_I2C_MXC 400 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 401 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 402 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 403 404 /* 405 * I2C bus multiplexer 406 */ 407 #define I2C_MUX_PCA_ADDR_PRI 0x77 408 #define I2C_MUX_CH_DEFAULT 0x8 409 #define I2C_MUX_CH_CH7301 0xC 410 411 /* 412 * MMC 413 */ 414 #define CONFIG_MMC 415 #define CONFIG_FSL_ESDHC 416 #define CONFIG_GENERIC_MMC 417 418 #define CONFIG_DOS_PARTITION 419 420 /* SPI */ 421 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 422 /* QSPI */ 423 #define QSPI0_AMBA_BASE 0x40000000 424 #define FSL_QSPI_FLASH_SIZE (1 << 24) 425 #define FSL_QSPI_FLASH_NUM 2 426 427 /* DSPI */ 428 429 /* DM SPI */ 430 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 431 #define CONFIG_DM_SPI_FLASH 432 #define CONFIG_SPI_FLASH_DATAFLASH 433 #endif 434 #endif 435 436 /* 437 * USB 438 */ 439 /* EHCI Support - disbaled by default */ 440 /*#define CONFIG_HAS_FSL_DR_USB*/ 441 442 #ifdef CONFIG_HAS_FSL_DR_USB 443 #define CONFIG_USB_EHCI 444 #define CONFIG_USB_EHCI_FSL 445 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 446 #endif 447 448 /*XHCI Support - enabled by default*/ 449 #define CONFIG_HAS_FSL_XHCI_USB 450 451 #ifdef CONFIG_HAS_FSL_XHCI_USB 452 #define CONFIG_USB_XHCI_FSL 453 #define CONFIG_USB_XHCI_DWC3 454 #define CONFIG_USB_XHCI 455 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 456 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 457 #endif 458 459 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB) 460 #define CONFIG_USB_STORAGE 461 #endif 462 463 /* 464 * Video 465 */ 466 #define CONFIG_FSL_DCU_FB 467 468 #ifdef CONFIG_FSL_DCU_FB 469 #define CONFIG_VIDEO 470 #define CONFIG_CMD_BMP 471 #define CONFIG_CFB_CONSOLE 472 #define CONFIG_VGA_AS_SINGLE_DEVICE 473 #define CONFIG_VIDEO_LOGO 474 #define CONFIG_VIDEO_BMP_LOGO 475 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 476 477 #define CONFIG_FSL_DIU_CH7301 478 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0 479 #define CONFIG_SYS_I2C_QIXIS_ADDR 0x66 480 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 481 #endif 482 483 /* 484 * eTSEC 485 */ 486 #define CONFIG_TSEC_ENET 487 488 #ifdef CONFIG_TSEC_ENET 489 #define CONFIG_MII 490 #define CONFIG_MII_DEFAULT_TSEC 3 491 #define CONFIG_TSEC1 1 492 #define CONFIG_TSEC1_NAME "eTSEC1" 493 #define CONFIG_TSEC2 1 494 #define CONFIG_TSEC2_NAME "eTSEC2" 495 #define CONFIG_TSEC3 1 496 #define CONFIG_TSEC3_NAME "eTSEC3" 497 498 #define TSEC1_PHY_ADDR 1 499 #define TSEC2_PHY_ADDR 2 500 #define TSEC3_PHY_ADDR 3 501 502 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 503 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 504 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 505 506 #define TSEC1_PHYIDX 0 507 #define TSEC2_PHYIDX 0 508 #define TSEC3_PHYIDX 0 509 510 #define CONFIG_ETHPRIME "eTSEC1" 511 512 #define CONFIG_PHY_GIGE 513 #define CONFIG_PHYLIB 514 #define CONFIG_PHY_REALTEK 515 516 #define CONFIG_HAS_ETH0 517 #define CONFIG_HAS_ETH1 518 #define CONFIG_HAS_ETH2 519 520 #define CONFIG_FSL_SGMII_RISER 1 521 #define SGMII_RISER_PHY_OFFSET 0x1b 522 523 #ifdef CONFIG_FSL_SGMII_RISER 524 #define CONFIG_SYS_TBIPA_VALUE 8 525 #endif 526 527 #endif 528 529 /* PCIe */ 530 #define CONFIG_PCI /* Enable PCI/PCIE */ 531 #define CONFIG_PCIE1 /* PCIE controller 1 */ 532 #define CONFIG_PCIE2 /* PCIE controller 2 */ 533 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 534 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" 535 536 #define CONFIG_SYS_PCI_64BIT 537 538 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 539 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ 540 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 541 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ 542 543 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 544 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 545 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ 546 547 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 548 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 549 #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ 550 551 #ifdef CONFIG_PCI 552 #define CONFIG_PCI_PNP 553 #define CONFIG_PCI_SCAN_SHOW 554 #define CONFIG_CMD_PCI 555 #endif 556 557 #define CONFIG_CMDLINE_TAG 558 #define CONFIG_CMDLINE_EDITING 559 560 #define CONFIG_ARMV7_NONSEC 561 #define CONFIG_ARMV7_VIRT 562 #define CONFIG_PEN_ADDR_BIG_ENDIAN 563 #define CONFIG_LAYERSCAPE_NS_ACCESS 564 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 565 #define CONFIG_TIMER_CLK_FREQ 12500000 566 567 #define CONFIG_HWCONFIG 568 #define HWCONFIG_BUFFER_SIZE 256 569 570 #define CONFIG_FSL_DEVICE_DISABLE 571 572 #define CONFIG_BOOTDELAY 3 573 574 #define CONFIG_SYS_QE_FW_ADDR 0x600c0000 575 576 #ifdef CONFIG_LPUART 577 #define CONFIG_EXTRA_ENV_SETTINGS \ 578 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ 579 "fdt_high=0xffffffff\0" \ 580 "initrd_high=0xffffffff\0" \ 581 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 582 #else 583 #define CONFIG_EXTRA_ENV_SETTINGS \ 584 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 585 "fdt_high=0xffffffff\0" \ 586 "initrd_high=0xffffffff\0" \ 587 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 588 #endif 589 590 /* 591 * Miscellaneous configurable options 592 */ 593 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 594 #define CONFIG_AUTO_COMPLETE 595 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 596 #define CONFIG_SYS_PBSIZE \ 597 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 598 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 599 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 600 601 #define CONFIG_SYS_MEMTEST_START 0x80000000 602 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 603 604 #define CONFIG_SYS_LOAD_ADDR 0x82000000 605 606 #define CONFIG_LS102XA_STREAM_ID 607 608 /* 609 * Stack sizes 610 * The stack sizes are set up in start.S using the settings below 611 */ 612 #define CONFIG_STACKSIZE (30 * 1024) 613 614 #define CONFIG_SYS_INIT_SP_OFFSET \ 615 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 616 #define CONFIG_SYS_INIT_SP_ADDR \ 617 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 618 619 #ifdef CONFIG_SPL_BUILD 620 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 621 #else 622 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 623 #endif 624 625 /* 626 * Environment 627 */ 628 #define CONFIG_ENV_OVERWRITE 629 630 #if defined(CONFIG_SD_BOOT) 631 #define CONFIG_ENV_OFFSET 0x100000 632 #define CONFIG_ENV_IS_IN_MMC 633 #define CONFIG_SYS_MMC_ENV_DEV 0 634 #define CONFIG_ENV_SIZE 0x2000 635 #elif defined(CONFIG_QSPI_BOOT) 636 #define CONFIG_ENV_IS_IN_SPI_FLASH 637 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 638 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 639 #define CONFIG_ENV_SECT_SIZE 0x10000 640 #elif defined(CONFIG_NAND_BOOT) 641 #define CONFIG_ENV_IS_IN_NAND 642 #define CONFIG_ENV_SIZE 0x2000 643 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 644 #else 645 #define CONFIG_ENV_IS_IN_FLASH 646 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 647 #define CONFIG_ENV_SIZE 0x2000 648 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 649 #endif 650 651 #define CONFIG_MISC_INIT_R 652 653 /* Hash command with SHA acceleration supported in hardware */ 654 #ifdef CONFIG_FSL_CAAM 655 #define CONFIG_CMD_HASH 656 #define CONFIG_SHA_HW_ACCEL 657 #endif 658 659 #include <asm/fsl_secure_boot.h> 660 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 661 662 #endif 663