1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_LS102XA 11 12 #define CONFIG_ARMV7_PSCI_1_0 13 14 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 15 16 #define CONFIG_SYS_FSL_CLK 17 18 #define CONFIG_SKIP_LOWLEVEL_INIT 19 #define CONFIG_BOARD_EARLY_INIT_F 20 21 #define CONFIG_DEEP_SLEEP 22 #if defined(CONFIG_DEEP_SLEEP) 23 #define CONFIG_SILENT_CONSOLE 24 #endif 25 26 /* 27 * Size of malloc() pool 28 */ 29 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 30 31 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 32 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 33 34 /* 35 * Generic Timer Definitions 36 */ 37 #define GENERIC_TIMER_CLK 12500000 38 39 #ifndef __ASSEMBLY__ 40 unsigned long get_board_sys_clk(void); 41 unsigned long get_board_ddr_clk(void); 42 #endif 43 44 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 45 #define CONFIG_SYS_CLK_FREQ 100000000 46 #define CONFIG_DDR_CLK_FREQ 100000000 47 #define CONFIG_QIXIS_I2C_ACCESS 48 #else 49 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 50 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 51 #endif 52 53 #ifdef CONFIG_RAMBOOT_PBL 54 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg 55 #endif 56 57 #ifdef CONFIG_SD_BOOT 58 #ifdef CONFIG_SD_BOOT_QSPI 59 #define CONFIG_SYS_FSL_PBL_RCW \ 60 board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg 61 #else 62 #define CONFIG_SYS_FSL_PBL_RCW \ 63 board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg 64 #endif 65 #define CONFIG_SPL_FRAMEWORK 66 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 67 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 68 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x600 69 70 #define CONFIG_SPL_TEXT_BASE 0x10000000 71 #define CONFIG_SPL_MAX_SIZE 0x1a000 72 #define CONFIG_SPL_STACK 0x1001d000 73 #define CONFIG_SPL_PAD_TO 0x1c000 74 #define CONFIG_SYS_TEXT_BASE 0x82000000 75 76 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 77 CONFIG_SYS_MONITOR_LEN) 78 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 79 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 80 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 81 #define CONFIG_SYS_MONITOR_LEN 0xc0000 82 #endif 83 84 #ifdef CONFIG_QSPI_BOOT 85 #define CONFIG_SYS_TEXT_BASE 0x40010000 86 #endif 87 88 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 89 #define CONFIG_SYS_NO_FLASH 90 #endif 91 92 #ifdef CONFIG_NAND_BOOT 93 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg 94 #define CONFIG_SPL_FRAMEWORK 95 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 96 97 #define CONFIG_SPL_TEXT_BASE 0x10000000 98 #define CONFIG_SPL_MAX_SIZE 0x1a000 99 #define CONFIG_SPL_STACK 0x1001d000 100 #define CONFIG_SPL_PAD_TO 0x1c000 101 #define CONFIG_SYS_TEXT_BASE 0x82000000 102 103 #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10) 104 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 105 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 106 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 107 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 108 109 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 110 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 111 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 112 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 113 #define CONFIG_SYS_MONITOR_LEN 0x80000 114 #endif 115 116 #ifndef CONFIG_SYS_TEXT_BASE 117 #define CONFIG_SYS_TEXT_BASE 0x60100000 118 #endif 119 120 #define CONFIG_NR_DRAM_BANKS 1 121 122 #define CONFIG_DDR_SPD 123 #define SPD_EEPROM_ADDRESS 0x51 124 #define CONFIG_SYS_SPD_BUS_NUM 0 125 126 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 127 #ifndef CONFIG_SYS_FSL_DDR4 128 #define CONFIG_SYS_DDR_RAW_TIMING 129 #endif 130 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 131 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 132 133 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 134 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 135 136 #define CONFIG_DDR_ECC 137 #ifdef CONFIG_DDR_ECC 138 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 139 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 140 #endif 141 142 #define CONFIG_FSL_CAAM /* Enable CAAM */ 143 144 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ 145 !defined(CONFIG_QSPI_BOOT) 146 #define CONFIG_U_QE 147 #endif 148 149 /* 150 * IFC Definitions 151 */ 152 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 153 #define CONFIG_FSL_IFC 154 #define CONFIG_SYS_FLASH_BASE 0x60000000 155 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 156 157 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 158 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 159 CSPR_PORT_SIZE_16 | \ 160 CSPR_MSEL_NOR | \ 161 CSPR_V) 162 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 163 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 164 + 0x8000000) | \ 165 CSPR_PORT_SIZE_16 | \ 166 CSPR_MSEL_NOR | \ 167 CSPR_V) 168 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 169 170 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 171 CSOR_NOR_TRHZ_80) 172 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 173 FTIM0_NOR_TEADC(0x5) | \ 174 FTIM0_NOR_TEAHC(0x5)) 175 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 176 FTIM1_NOR_TRAD_NOR(0x1a) | \ 177 FTIM1_NOR_TSEQRAD_NOR(0x13)) 178 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 179 FTIM2_NOR_TCH(0x4) | \ 180 FTIM2_NOR_TWPH(0xe) | \ 181 FTIM2_NOR_TWP(0x1c)) 182 #define CONFIG_SYS_NOR_FTIM3 0 183 184 #define CONFIG_FLASH_CFI_DRIVER 185 #define CONFIG_SYS_FLASH_CFI 186 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 187 #define CONFIG_SYS_FLASH_QUIET_TEST 188 #define CONFIG_FLASH_SHOW_PROGRESS 45 189 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 190 #define CONFIG_SYS_WRITE_SWAPPED_DATA 191 192 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 193 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 194 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 195 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 196 197 #define CONFIG_SYS_FLASH_EMPTY_INFO 198 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 199 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 200 201 /* 202 * NAND Flash Definitions 203 */ 204 #define CONFIG_NAND_FSL_IFC 205 206 #define CONFIG_SYS_NAND_BASE 0x7e800000 207 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 208 209 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 210 211 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 212 | CSPR_PORT_SIZE_8 \ 213 | CSPR_MSEL_NAND \ 214 | CSPR_V) 215 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 216 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 217 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 218 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 219 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 220 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 221 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 222 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 223 224 #define CONFIG_SYS_NAND_ONFI_DETECTION 225 226 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 227 FTIM0_NAND_TWP(0x18) | \ 228 FTIM0_NAND_TWCHT(0x7) | \ 229 FTIM0_NAND_TWH(0xa)) 230 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 231 FTIM1_NAND_TWBE(0x39) | \ 232 FTIM1_NAND_TRR(0xe) | \ 233 FTIM1_NAND_TRP(0x18)) 234 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 235 FTIM2_NAND_TREH(0xa) | \ 236 FTIM2_NAND_TWHRE(0x1e)) 237 #define CONFIG_SYS_NAND_FTIM3 0x0 238 239 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 240 #define CONFIG_SYS_MAX_NAND_DEVICE 1 241 #define CONFIG_CMD_NAND 242 243 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 244 #endif 245 246 /* 247 * QIXIS Definitions 248 */ 249 #define CONFIG_FSL_QIXIS 250 251 #ifdef CONFIG_FSL_QIXIS 252 #define QIXIS_BASE 0x7fb00000 253 #define QIXIS_BASE_PHYS QIXIS_BASE 254 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 255 #define QIXIS_LBMAP_SWITCH 6 256 #define QIXIS_LBMAP_MASK 0x0f 257 #define QIXIS_LBMAP_SHIFT 0 258 #define QIXIS_LBMAP_DFLTBANK 0x00 259 #define QIXIS_LBMAP_ALTBANK 0x04 260 #define QIXIS_PWR_CTL 0x21 261 #define QIXIS_PWR_CTL_POWEROFF 0x80 262 #define QIXIS_RST_CTL_RESET 0x44 263 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 264 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 265 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 266 #define QIXIS_CTL_SYS 0x5 267 #define QIXIS_CTL_SYS_EVTSW_MASK 0x0c 268 #define QIXIS_CTL_SYS_EVTSW_IRQ 0x04 269 #define QIXIS_RST_FORCE_3 0x45 270 #define QIXIS_RST_FORCE_3_PCIESLOT1 0x80 271 #define QIXIS_PWR_CTL2 0x21 272 #define QIXIS_PWR_CTL2_PCTL 0x2 273 274 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 275 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 276 CSPR_PORT_SIZE_8 | \ 277 CSPR_MSEL_GPCM | \ 278 CSPR_V) 279 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 280 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 281 CSOR_NOR_NOR_MODE_AVD_NOR | \ 282 CSOR_NOR_TRHZ_80) 283 284 /* 285 * QIXIS Timing parameters for IFC GPCM 286 */ 287 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \ 288 FTIM0_GPCM_TEADC(0xe) | \ 289 FTIM0_GPCM_TEAHC(0xe)) 290 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \ 291 FTIM1_GPCM_TRAD(0x1f)) 292 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \ 293 FTIM2_GPCM_TCH(0xe) | \ 294 FTIM2_GPCM_TWP(0xf0)) 295 #define CONFIG_SYS_FPGA_FTIM3 0x0 296 #endif 297 298 #if defined(CONFIG_NAND_BOOT) 299 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 300 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 301 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 302 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 303 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 304 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 305 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 306 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 307 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 308 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 309 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 310 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 311 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 312 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 313 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 314 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 315 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 316 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 317 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 318 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 319 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 320 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 321 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 322 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 323 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 324 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 325 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 326 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 327 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 328 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 329 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 330 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 331 #else 332 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 333 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 334 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 335 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 336 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 337 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 338 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 339 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 340 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 341 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 342 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 343 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 344 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 345 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 346 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 347 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 348 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 349 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 350 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 351 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 352 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 353 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 354 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 355 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 356 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 357 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 358 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 359 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 360 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 361 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 362 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 363 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 364 #endif 365 366 /* 367 * Serial Port 368 */ 369 #ifdef CONFIG_LPUART 370 #define CONFIG_LPUART_32B_REG 371 #else 372 #define CONFIG_CONS_INDEX 1 373 #define CONFIG_SYS_NS16550_SERIAL 374 #ifndef CONFIG_DM_SERIAL 375 #define CONFIG_SYS_NS16550_REG_SIZE 1 376 #endif 377 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 378 #endif 379 380 #define CONFIG_BAUDRATE 115200 381 382 /* 383 * I2C 384 */ 385 #define CONFIG_SYS_I2C 386 #define CONFIG_SYS_I2C_MXC 387 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 388 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 389 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 390 391 /* 392 * I2C bus multiplexer 393 */ 394 #define I2C_MUX_PCA_ADDR_PRI 0x77 395 #define I2C_MUX_CH_DEFAULT 0x8 396 #define I2C_MUX_CH_CH7301 0xC 397 398 /* 399 * MMC 400 */ 401 #define CONFIG_MMC 402 #define CONFIG_FSL_ESDHC 403 #define CONFIG_GENERIC_MMC 404 405 #define CONFIG_DOS_PARTITION 406 407 /* SPI */ 408 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 409 /* QSPI */ 410 #define QSPI0_AMBA_BASE 0x40000000 411 #define FSL_QSPI_FLASH_SIZE (1 << 24) 412 #define FSL_QSPI_FLASH_NUM 2 413 414 /* DSPI */ 415 416 /* DM SPI */ 417 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 418 #define CONFIG_DM_SPI_FLASH 419 #define CONFIG_SPI_FLASH_DATAFLASH 420 #endif 421 #endif 422 423 /* 424 * USB 425 */ 426 /* EHCI Support - disbaled by default */ 427 /*#define CONFIG_HAS_FSL_DR_USB*/ 428 429 #ifdef CONFIG_HAS_FSL_DR_USB 430 #define CONFIG_USB_EHCI 431 #define CONFIG_USB_EHCI_FSL 432 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 433 #endif 434 435 /*XHCI Support - enabled by default*/ 436 #define CONFIG_HAS_FSL_XHCI_USB 437 438 #ifdef CONFIG_HAS_FSL_XHCI_USB 439 #define CONFIG_USB_XHCI_FSL 440 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 441 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 442 #endif 443 444 /* 445 * Video 446 */ 447 #define CONFIG_FSL_DCU_FB 448 449 #ifdef CONFIG_FSL_DCU_FB 450 #define CONFIG_VIDEO 451 #define CONFIG_CMD_BMP 452 #define CONFIG_CFB_CONSOLE 453 #define CONFIG_VGA_AS_SINGLE_DEVICE 454 #define CONFIG_VIDEO_LOGO 455 #define CONFIG_VIDEO_BMP_LOGO 456 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 457 458 #define CONFIG_FSL_DIU_CH7301 459 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0 460 #define CONFIG_SYS_I2C_QIXIS_ADDR 0x66 461 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 462 #endif 463 464 /* 465 * eTSEC 466 */ 467 #define CONFIG_TSEC_ENET 468 469 #ifdef CONFIG_TSEC_ENET 470 #define CONFIG_MII 471 #define CONFIG_MII_DEFAULT_TSEC 3 472 #define CONFIG_TSEC1 1 473 #define CONFIG_TSEC1_NAME "eTSEC1" 474 #define CONFIG_TSEC2 1 475 #define CONFIG_TSEC2_NAME "eTSEC2" 476 #define CONFIG_TSEC3 1 477 #define CONFIG_TSEC3_NAME "eTSEC3" 478 479 #define TSEC1_PHY_ADDR 1 480 #define TSEC2_PHY_ADDR 2 481 #define TSEC3_PHY_ADDR 3 482 483 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 484 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 485 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 486 487 #define TSEC1_PHYIDX 0 488 #define TSEC2_PHYIDX 0 489 #define TSEC3_PHYIDX 0 490 491 #define CONFIG_ETHPRIME "eTSEC1" 492 493 #define CONFIG_PHY_GIGE 494 #define CONFIG_PHYLIB 495 #define CONFIG_PHY_REALTEK 496 497 #define CONFIG_HAS_ETH0 498 #define CONFIG_HAS_ETH1 499 #define CONFIG_HAS_ETH2 500 501 #define CONFIG_FSL_SGMII_RISER 1 502 #define SGMII_RISER_PHY_OFFSET 0x1b 503 504 #ifdef CONFIG_FSL_SGMII_RISER 505 #define CONFIG_SYS_TBIPA_VALUE 8 506 #endif 507 508 #endif 509 510 /* PCIe */ 511 #define CONFIG_PCI /* Enable PCI/PCIE */ 512 #define CONFIG_PCIE1 /* PCIE controller 1 */ 513 #define CONFIG_PCIE2 /* PCIE controller 2 */ 514 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 515 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" 516 517 #define CONFIG_SYS_PCI_64BIT 518 519 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 520 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ 521 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 522 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ 523 524 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 525 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 526 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ 527 528 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 529 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 530 #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ 531 532 #ifdef CONFIG_PCI 533 #define CONFIG_PCI_PNP 534 #define CONFIG_PCI_SCAN_SHOW 535 #define CONFIG_CMD_PCI 536 #endif 537 538 #define CONFIG_CMDLINE_TAG 539 #define CONFIG_CMDLINE_EDITING 540 541 #define CONFIG_PEN_ADDR_BIG_ENDIAN 542 #define CONFIG_LAYERSCAPE_NS_ACCESS 543 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 544 #define CONFIG_TIMER_CLK_FREQ 12500000 545 546 #define CONFIG_HWCONFIG 547 #define HWCONFIG_BUFFER_SIZE 256 548 549 #define CONFIG_FSL_DEVICE_DISABLE 550 551 552 #define CONFIG_SYS_QE_FW_ADDR 0x600c0000 553 554 #ifdef CONFIG_LPUART 555 #define CONFIG_EXTRA_ENV_SETTINGS \ 556 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ 557 "fdt_high=0xffffffff\0" \ 558 "initrd_high=0xffffffff\0" \ 559 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 560 #else 561 #define CONFIG_EXTRA_ENV_SETTINGS \ 562 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 563 "fdt_high=0xffffffff\0" \ 564 "initrd_high=0xffffffff\0" \ 565 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 566 #endif 567 568 /* 569 * Miscellaneous configurable options 570 */ 571 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 572 #define CONFIG_AUTO_COMPLETE 573 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 574 #define CONFIG_SYS_PBSIZE \ 575 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 576 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 577 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 578 579 #define CONFIG_SYS_MEMTEST_START 0x80000000 580 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 581 582 #define CONFIG_SYS_LOAD_ADDR 0x82000000 583 584 #define CONFIG_LS102XA_STREAM_ID 585 586 /* 587 * Stack sizes 588 * The stack sizes are set up in start.S using the settings below 589 */ 590 #define CONFIG_STACKSIZE (30 * 1024) 591 592 #define CONFIG_SYS_INIT_SP_OFFSET \ 593 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 594 #define CONFIG_SYS_INIT_SP_ADDR \ 595 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 596 597 #ifdef CONFIG_SPL_BUILD 598 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 599 #else 600 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 601 #endif 602 603 /* 604 * Environment 605 */ 606 #define CONFIG_ENV_OVERWRITE 607 608 #if defined(CONFIG_SD_BOOT) 609 #define CONFIG_ENV_OFFSET 0x100000 610 #define CONFIG_ENV_IS_IN_MMC 611 #define CONFIG_SYS_MMC_ENV_DEV 0 612 #define CONFIG_ENV_SIZE 0x2000 613 #elif defined(CONFIG_QSPI_BOOT) 614 #define CONFIG_ENV_IS_IN_SPI_FLASH 615 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 616 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 617 #define CONFIG_ENV_SECT_SIZE 0x10000 618 #elif defined(CONFIG_NAND_BOOT) 619 #define CONFIG_ENV_IS_IN_NAND 620 #define CONFIG_ENV_SIZE 0x2000 621 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 622 #else 623 #define CONFIG_ENV_IS_IN_FLASH 624 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 625 #define CONFIG_ENV_SIZE 0x2000 626 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 627 #endif 628 629 #define CONFIG_MISC_INIT_R 630 631 /* Hash command with SHA acceleration supported in hardware */ 632 #ifdef CONFIG_FSL_CAAM 633 #define CONFIG_CMD_HASH 634 #define CONFIG_SHA_HW_ACCEL 635 #endif 636 637 #include <asm/fsl_secure_boot.h> 638 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 639 640 #endif 641