1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_LS102XA 11 12 #define CONFIG_ARMV7_PSCI_1_0 13 14 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 15 16 #define CONFIG_SYS_FSL_CLK 17 18 #define CONFIG_SKIP_LOWLEVEL_INIT 19 20 #define CONFIG_DEEP_SLEEP 21 22 /* 23 * Size of malloc() pool 24 */ 25 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 26 27 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 28 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 29 30 /* 31 * Generic Timer Definitions 32 */ 33 #define GENERIC_TIMER_CLK 12500000 34 35 #ifndef __ASSEMBLY__ 36 unsigned long get_board_sys_clk(void); 37 unsigned long get_board_ddr_clk(void); 38 #endif 39 40 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 41 #define CONFIG_SYS_CLK_FREQ 100000000 42 #define CONFIG_DDR_CLK_FREQ 100000000 43 #define CONFIG_QIXIS_I2C_ACCESS 44 #else 45 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 46 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 47 #endif 48 49 #ifdef CONFIG_RAMBOOT_PBL 50 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg 51 #endif 52 53 #ifdef CONFIG_SD_BOOT 54 #ifdef CONFIG_SD_BOOT_QSPI 55 #define CONFIG_SYS_FSL_PBL_RCW \ 56 board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg 57 #else 58 #define CONFIG_SYS_FSL_PBL_RCW \ 59 board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg 60 #endif 61 #define CONFIG_SPL_FRAMEWORK 62 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 63 64 #define CONFIG_SPL_TEXT_BASE 0x10000000 65 #define CONFIG_SPL_MAX_SIZE 0x1a000 66 #define CONFIG_SPL_STACK 0x1001d000 67 #define CONFIG_SPL_PAD_TO 0x1c000 68 #define CONFIG_SYS_TEXT_BASE 0x82000000 69 70 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 71 CONFIG_SYS_MONITOR_LEN) 72 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 73 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 74 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 75 #define CONFIG_SYS_MONITOR_LEN 0xc0000 76 #endif 77 78 #ifdef CONFIG_QSPI_BOOT 79 #define CONFIG_SYS_TEXT_BASE 0x40010000 80 #endif 81 82 #ifdef CONFIG_NAND_BOOT 83 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg 84 #define CONFIG_SPL_FRAMEWORK 85 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 86 87 #define CONFIG_SPL_TEXT_BASE 0x10000000 88 #define CONFIG_SPL_MAX_SIZE 0x1a000 89 #define CONFIG_SPL_STACK 0x1001d000 90 #define CONFIG_SPL_PAD_TO 0x1c000 91 #define CONFIG_SYS_TEXT_BASE 0x82000000 92 93 #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10) 94 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 95 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 96 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 97 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 98 99 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 100 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 101 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 102 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 103 #define CONFIG_SYS_MONITOR_LEN 0x80000 104 #endif 105 106 #ifndef CONFIG_SYS_TEXT_BASE 107 #define CONFIG_SYS_TEXT_BASE 0x60100000 108 #endif 109 110 #define CONFIG_NR_DRAM_BANKS 1 111 112 #define CONFIG_DDR_SPD 113 #define SPD_EEPROM_ADDRESS 0x51 114 #define CONFIG_SYS_SPD_BUS_NUM 0 115 116 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 117 #ifndef CONFIG_SYS_FSL_DDR4 118 #define CONFIG_SYS_DDR_RAW_TIMING 119 #endif 120 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 121 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 122 123 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 124 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 125 126 #define CONFIG_DDR_ECC 127 #ifdef CONFIG_DDR_ECC 128 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 129 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 130 #endif 131 132 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ 133 !defined(CONFIG_QSPI_BOOT) 134 #define CONFIG_U_QE 135 #endif 136 137 /* 138 * IFC Definitions 139 */ 140 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 141 #define CONFIG_FSL_IFC 142 #define CONFIG_SYS_FLASH_BASE 0x60000000 143 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 144 145 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 146 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 147 CSPR_PORT_SIZE_16 | \ 148 CSPR_MSEL_NOR | \ 149 CSPR_V) 150 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 151 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 152 + 0x8000000) | \ 153 CSPR_PORT_SIZE_16 | \ 154 CSPR_MSEL_NOR | \ 155 CSPR_V) 156 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 157 158 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 159 CSOR_NOR_TRHZ_80) 160 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 161 FTIM0_NOR_TEADC(0x5) | \ 162 FTIM0_NOR_TEAHC(0x5)) 163 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 164 FTIM1_NOR_TRAD_NOR(0x1a) | \ 165 FTIM1_NOR_TSEQRAD_NOR(0x13)) 166 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 167 FTIM2_NOR_TCH(0x4) | \ 168 FTIM2_NOR_TWPH(0xe) | \ 169 FTIM2_NOR_TWP(0x1c)) 170 #define CONFIG_SYS_NOR_FTIM3 0 171 172 #define CONFIG_FLASH_CFI_DRIVER 173 #define CONFIG_SYS_FLASH_CFI 174 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 175 #define CONFIG_SYS_FLASH_QUIET_TEST 176 #define CONFIG_FLASH_SHOW_PROGRESS 45 177 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 178 #define CONFIG_SYS_WRITE_SWAPPED_DATA 179 180 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 181 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 182 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 183 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 184 185 #define CONFIG_SYS_FLASH_EMPTY_INFO 186 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 187 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 188 189 /* 190 * NAND Flash Definitions 191 */ 192 #define CONFIG_NAND_FSL_IFC 193 194 #define CONFIG_SYS_NAND_BASE 0x7e800000 195 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 196 197 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 198 199 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 200 | CSPR_PORT_SIZE_8 \ 201 | CSPR_MSEL_NAND \ 202 | CSPR_V) 203 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 204 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 205 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 206 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 207 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 208 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 209 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 210 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 211 212 #define CONFIG_SYS_NAND_ONFI_DETECTION 213 214 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 215 FTIM0_NAND_TWP(0x18) | \ 216 FTIM0_NAND_TWCHT(0x7) | \ 217 FTIM0_NAND_TWH(0xa)) 218 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 219 FTIM1_NAND_TWBE(0x39) | \ 220 FTIM1_NAND_TRR(0xe) | \ 221 FTIM1_NAND_TRP(0x18)) 222 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 223 FTIM2_NAND_TREH(0xa) | \ 224 FTIM2_NAND_TWHRE(0x1e)) 225 #define CONFIG_SYS_NAND_FTIM3 0x0 226 227 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 228 #define CONFIG_SYS_MAX_NAND_DEVICE 1 229 #define CONFIG_CMD_NAND 230 231 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 232 #endif 233 234 /* 235 * QIXIS Definitions 236 */ 237 #define CONFIG_FSL_QIXIS 238 239 #ifdef CONFIG_FSL_QIXIS 240 #define QIXIS_BASE 0x7fb00000 241 #define QIXIS_BASE_PHYS QIXIS_BASE 242 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 243 #define QIXIS_LBMAP_SWITCH 6 244 #define QIXIS_LBMAP_MASK 0x0f 245 #define QIXIS_LBMAP_SHIFT 0 246 #define QIXIS_LBMAP_DFLTBANK 0x00 247 #define QIXIS_LBMAP_ALTBANK 0x04 248 #define QIXIS_PWR_CTL 0x21 249 #define QIXIS_PWR_CTL_POWEROFF 0x80 250 #define QIXIS_RST_CTL_RESET 0x44 251 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 252 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 253 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 254 #define QIXIS_CTL_SYS 0x5 255 #define QIXIS_CTL_SYS_EVTSW_MASK 0x0c 256 #define QIXIS_CTL_SYS_EVTSW_IRQ 0x04 257 #define QIXIS_RST_FORCE_3 0x45 258 #define QIXIS_RST_FORCE_3_PCIESLOT1 0x80 259 #define QIXIS_PWR_CTL2 0x21 260 #define QIXIS_PWR_CTL2_PCTL 0x2 261 262 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 263 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 264 CSPR_PORT_SIZE_8 | \ 265 CSPR_MSEL_GPCM | \ 266 CSPR_V) 267 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 268 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 269 CSOR_NOR_NOR_MODE_AVD_NOR | \ 270 CSOR_NOR_TRHZ_80) 271 272 /* 273 * QIXIS Timing parameters for IFC GPCM 274 */ 275 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \ 276 FTIM0_GPCM_TEADC(0xe) | \ 277 FTIM0_GPCM_TEAHC(0xe)) 278 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \ 279 FTIM1_GPCM_TRAD(0x1f)) 280 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \ 281 FTIM2_GPCM_TCH(0xe) | \ 282 FTIM2_GPCM_TWP(0xf0)) 283 #define CONFIG_SYS_FPGA_FTIM3 0x0 284 #endif 285 286 #if defined(CONFIG_NAND_BOOT) 287 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 288 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 289 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 290 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 291 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 292 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 293 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 294 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 295 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 296 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 297 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 298 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 299 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 300 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 301 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 302 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 303 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 304 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 305 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 306 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 307 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 308 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 309 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 310 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 311 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 312 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 313 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 314 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 315 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 316 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 317 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 318 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 319 #else 320 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 321 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 322 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 323 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 324 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 325 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 326 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 327 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 328 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 329 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 330 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 331 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 332 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 333 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 334 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 335 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 336 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 337 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 338 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 339 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 340 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 341 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 342 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 343 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 344 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 345 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 346 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 347 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 348 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 349 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 350 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 351 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 352 #endif 353 354 /* 355 * Serial Port 356 */ 357 #ifdef CONFIG_LPUART 358 #define CONFIG_LPUART_32B_REG 359 #else 360 #define CONFIG_CONS_INDEX 1 361 #define CONFIG_SYS_NS16550_SERIAL 362 #ifndef CONFIG_DM_SERIAL 363 #define CONFIG_SYS_NS16550_REG_SIZE 1 364 #endif 365 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 366 #endif 367 368 /* 369 * I2C 370 */ 371 #define CONFIG_SYS_I2C 372 #define CONFIG_SYS_I2C_MXC 373 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 374 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 375 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 376 377 /* 378 * I2C bus multiplexer 379 */ 380 #define I2C_MUX_PCA_ADDR_PRI 0x77 381 #define I2C_MUX_CH_DEFAULT 0x8 382 #define I2C_MUX_CH_CH7301 0xC 383 384 /* 385 * MMC 386 */ 387 #define CONFIG_FSL_ESDHC 388 389 /* SPI */ 390 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 391 /* QSPI */ 392 #define QSPI0_AMBA_BASE 0x40000000 393 #define FSL_QSPI_FLASH_SIZE (1 << 24) 394 #define FSL_QSPI_FLASH_NUM 2 395 396 /* DSPI */ 397 398 /* DM SPI */ 399 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 400 #define CONFIG_DM_SPI_FLASH 401 #define CONFIG_SPI_FLASH_DATAFLASH 402 #endif 403 #endif 404 405 /* 406 * USB 407 */ 408 /* EHCI Support - disbaled by default */ 409 /*#define CONFIG_HAS_FSL_DR_USB*/ 410 411 #ifdef CONFIG_HAS_FSL_DR_USB 412 #define CONFIG_USB_EHCI 413 #define CONFIG_USB_EHCI_FSL 414 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 415 #endif 416 417 /*XHCI Support - enabled by default*/ 418 #define CONFIG_HAS_FSL_XHCI_USB 419 420 #ifdef CONFIG_HAS_FSL_XHCI_USB 421 #define CONFIG_USB_XHCI_FSL 422 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 423 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 424 #endif 425 426 /* 427 * Video 428 */ 429 #define CONFIG_FSL_DCU_FB 430 431 #ifdef CONFIG_FSL_DCU_FB 432 #define CONFIG_CMD_BMP 433 #define CONFIG_VIDEO_LOGO 434 #define CONFIG_VIDEO_BMP_LOGO 435 436 #define CONFIG_FSL_DIU_CH7301 437 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0 438 #define CONFIG_SYS_I2C_QIXIS_ADDR 0x66 439 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 440 #endif 441 442 /* 443 * eTSEC 444 */ 445 #define CONFIG_TSEC_ENET 446 447 #ifdef CONFIG_TSEC_ENET 448 #define CONFIG_MII 449 #define CONFIG_MII_DEFAULT_TSEC 3 450 #define CONFIG_TSEC1 1 451 #define CONFIG_TSEC1_NAME "eTSEC1" 452 #define CONFIG_TSEC2 1 453 #define CONFIG_TSEC2_NAME "eTSEC2" 454 #define CONFIG_TSEC3 1 455 #define CONFIG_TSEC3_NAME "eTSEC3" 456 457 #define TSEC1_PHY_ADDR 1 458 #define TSEC2_PHY_ADDR 2 459 #define TSEC3_PHY_ADDR 3 460 461 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 462 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 463 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 464 465 #define TSEC1_PHYIDX 0 466 #define TSEC2_PHYIDX 0 467 #define TSEC3_PHYIDX 0 468 469 #define CONFIG_ETHPRIME "eTSEC1" 470 471 #define CONFIG_PHY_GIGE 472 #define CONFIG_PHYLIB 473 #define CONFIG_PHY_REALTEK 474 475 #define CONFIG_HAS_ETH0 476 #define CONFIG_HAS_ETH1 477 #define CONFIG_HAS_ETH2 478 479 #define CONFIG_FSL_SGMII_RISER 1 480 #define SGMII_RISER_PHY_OFFSET 0x1b 481 482 #ifdef CONFIG_FSL_SGMII_RISER 483 #define CONFIG_SYS_TBIPA_VALUE 8 484 #endif 485 486 #endif 487 488 /* PCIe */ 489 #define CONFIG_PCIE1 /* PCIE controller 1 */ 490 #define CONFIG_PCIE2 /* PCIE controller 2 */ 491 492 #ifdef CONFIG_PCI 493 #define CONFIG_PCI_SCAN_SHOW 494 #define CONFIG_CMD_PCI 495 #endif 496 497 #define CONFIG_CMDLINE_TAG 498 #define CONFIG_CMDLINE_EDITING 499 500 #define CONFIG_PEN_ADDR_BIG_ENDIAN 501 #define CONFIG_LAYERSCAPE_NS_ACCESS 502 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 503 #define CONFIG_TIMER_CLK_FREQ 12500000 504 505 #define CONFIG_HWCONFIG 506 #define HWCONFIG_BUFFER_SIZE 256 507 508 #define CONFIG_FSL_DEVICE_DISABLE 509 510 511 #define CONFIG_SYS_QE_FW_ADDR 0x600c0000 512 513 #ifdef CONFIG_LPUART 514 #define CONFIG_EXTRA_ENV_SETTINGS \ 515 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ 516 "fdt_high=0xffffffff\0" \ 517 "initrd_high=0xffffffff\0" \ 518 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 519 #else 520 #define CONFIG_EXTRA_ENV_SETTINGS \ 521 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 522 "fdt_high=0xffffffff\0" \ 523 "initrd_high=0xffffffff\0" \ 524 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 525 #endif 526 527 /* 528 * Miscellaneous configurable options 529 */ 530 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 531 #define CONFIG_AUTO_COMPLETE 532 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 533 #define CONFIG_SYS_PBSIZE \ 534 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 535 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 536 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 537 538 #define CONFIG_SYS_MEMTEST_START 0x80000000 539 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 540 541 #define CONFIG_SYS_LOAD_ADDR 0x82000000 542 543 #define CONFIG_LS102XA_STREAM_ID 544 545 /* 546 * Stack sizes 547 * The stack sizes are set up in start.S using the settings below 548 */ 549 #define CONFIG_STACKSIZE (30 * 1024) 550 551 #define CONFIG_SYS_INIT_SP_OFFSET \ 552 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 553 #define CONFIG_SYS_INIT_SP_ADDR \ 554 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 555 556 #ifdef CONFIG_SPL_BUILD 557 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 558 #else 559 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 560 #endif 561 562 /* 563 * Environment 564 */ 565 #define CONFIG_ENV_OVERWRITE 566 567 #if defined(CONFIG_SD_BOOT) 568 #define CONFIG_ENV_OFFSET 0x100000 569 #define CONFIG_ENV_IS_IN_MMC 570 #define CONFIG_SYS_MMC_ENV_DEV 0 571 #define CONFIG_ENV_SIZE 0x2000 572 #elif defined(CONFIG_QSPI_BOOT) 573 #define CONFIG_ENV_IS_IN_SPI_FLASH 574 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 575 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 576 #define CONFIG_ENV_SECT_SIZE 0x10000 577 #elif defined(CONFIG_NAND_BOOT) 578 #define CONFIG_ENV_IS_IN_NAND 579 #define CONFIG_ENV_SIZE 0x2000 580 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 581 #else 582 #define CONFIG_ENV_IS_IN_FLASH 583 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 584 #define CONFIG_ENV_SIZE 0x2000 585 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 586 #endif 587 588 #define CONFIG_MISC_INIT_R 589 590 /* Hash command with SHA acceleration supported in hardware */ 591 #ifdef CONFIG_FSL_CAAM 592 #define CONFIG_CMD_HASH 593 #define CONFIG_SHA_HW_ACCEL 594 #endif 595 596 #include <asm/fsl_secure_boot.h> 597 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 598 599 #endif 600