1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #include <config_cmd_default.h> 11 12 #define CONFIG_LS102XA 13 14 #define CONFIG_SYS_GENERIC_BOARD 15 16 #define CONFIG_DISPLAY_CPUINFO 17 #define CONFIG_DISPLAY_BOARDINFO 18 19 #define CONFIG_SKIP_LOWLEVEL_INIT 20 #define CONFIG_BOARD_EARLY_INIT_F 21 22 /* 23 * Size of malloc() pool 24 */ 25 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 26 27 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 28 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 29 30 /* 31 * Generic Timer Definitions 32 */ 33 #define GENERIC_TIMER_CLK 12500000 34 35 #ifndef __ASSEMBLY__ 36 unsigned long get_board_sys_clk(void); 37 unsigned long get_board_ddr_clk(void); 38 #endif 39 40 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 41 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 42 43 #ifndef CONFIG_SYS_TEXT_BASE 44 #define CONFIG_SYS_TEXT_BASE 0x67f80000 45 #endif 46 47 #define CONFIG_NR_DRAM_BANKS 1 48 49 #define CONFIG_DDR_SPD 50 #define SPD_EEPROM_ADDRESS 0x51 51 #define CONFIG_SYS_SPD_BUS_NUM 0 52 53 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 54 #ifndef CONFIG_SYS_FSL_DDR4 55 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ 56 #define CONFIG_SYS_DDR_RAW_TIMING 57 #endif 58 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 59 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 60 61 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 62 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 63 64 #define CONFIG_DDR_ECC 65 #ifdef CONFIG_DDR_ECC 66 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 67 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 68 #endif 69 70 #define CONFIG_SYS_HAS_SERDES 71 72 #define CONFIG_FSL_CAAM /* Enable CAAM */ 73 74 #if !defined(CONFIG_SDCARD) && !defined(CONFIG_NAND) && !defined(CONFIG_SPI) 75 #define CONFIG_U_QE 76 #endif 77 78 /* 79 * IFC Definitions 80 */ 81 #define CONFIG_FSL_IFC 82 #define CONFIG_SYS_FLASH_BASE 0x60000000 83 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 84 85 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 86 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 87 CSPR_PORT_SIZE_16 | \ 88 CSPR_MSEL_NOR | \ 89 CSPR_V) 90 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 91 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 92 + 0x8000000) | \ 93 CSPR_PORT_SIZE_16 | \ 94 CSPR_MSEL_NOR | \ 95 CSPR_V) 96 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 97 98 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 99 CSOR_NOR_TRHZ_80) 100 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 101 FTIM0_NOR_TEADC(0x5) | \ 102 FTIM0_NOR_TEAHC(0x5)) 103 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 104 FTIM1_NOR_TRAD_NOR(0x1a) | \ 105 FTIM1_NOR_TSEQRAD_NOR(0x13)) 106 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 107 FTIM2_NOR_TCH(0x4) | \ 108 FTIM2_NOR_TWPH(0xe) | \ 109 FTIM2_NOR_TWP(0x1c)) 110 #define CONFIG_SYS_NOR_FTIM3 0 111 112 #define CONFIG_FLASH_CFI_DRIVER 113 #define CONFIG_SYS_FLASH_CFI 114 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 115 #define CONFIG_SYS_FLASH_QUIET_TEST 116 #define CONFIG_FLASH_SHOW_PROGRESS 45 117 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 118 119 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 120 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 121 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 122 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 123 124 #define CONFIG_SYS_FLASH_EMPTY_INFO 125 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 126 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 127 128 /* 129 * NAND Flash Definitions 130 */ 131 #define CONFIG_NAND_FSL_IFC 132 133 #define CONFIG_SYS_NAND_BASE 0x7e800000 134 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 135 136 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 137 138 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 139 | CSPR_PORT_SIZE_8 \ 140 | CSPR_MSEL_NAND \ 141 | CSPR_V) 142 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 143 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 144 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 145 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 146 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 147 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 148 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 149 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 150 151 #define CONFIG_SYS_NAND_ONFI_DETECTION 152 153 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 154 FTIM0_NAND_TWP(0x18) | \ 155 FTIM0_NAND_TWCHT(0x7) | \ 156 FTIM0_NAND_TWH(0xa)) 157 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 158 FTIM1_NAND_TWBE(0x39) | \ 159 FTIM1_NAND_TRR(0xe) | \ 160 FTIM1_NAND_TRP(0x18)) 161 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 162 FTIM2_NAND_TREH(0xa) | \ 163 FTIM2_NAND_TWHRE(0x1e)) 164 #define CONFIG_SYS_NAND_FTIM3 0x0 165 166 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 167 #define CONFIG_SYS_MAX_NAND_DEVICE 1 168 #define CONFIG_MTD_NAND_VERIFY_WRITE 169 #define CONFIG_CMD_NAND 170 171 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 172 173 /* 174 * QIXIS Definitions 175 */ 176 #define CONFIG_FSL_QIXIS 177 178 #ifdef CONFIG_FSL_QIXIS 179 #define QIXIS_BASE 0x7fb00000 180 #define QIXIS_BASE_PHYS QIXIS_BASE 181 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 182 #define QIXIS_LBMAP_SWITCH 6 183 #define QIXIS_LBMAP_MASK 0x0f 184 #define QIXIS_LBMAP_SHIFT 0 185 #define QIXIS_LBMAP_DFLTBANK 0x00 186 #define QIXIS_LBMAP_ALTBANK 0x04 187 #define QIXIS_RST_CTL_RESET 0x44 188 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 189 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 190 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 191 192 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 193 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 194 CSPR_PORT_SIZE_8 | \ 195 CSPR_MSEL_GPCM | \ 196 CSPR_V) 197 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 198 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 199 CSOR_NOR_NOR_MODE_AVD_NOR | \ 200 CSOR_NOR_TRHZ_80) 201 202 /* 203 * QIXIS Timing parameters for IFC GPCM 204 */ 205 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \ 206 FTIM0_GPCM_TEADC(0xe) | \ 207 FTIM0_GPCM_TEAHC(0xe)) 208 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \ 209 FTIM1_GPCM_TRAD(0x1f)) 210 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \ 211 FTIM2_GPCM_TCH(0xe) | \ 212 FTIM2_GPCM_TWP(0xf0)) 213 #define CONFIG_SYS_FPGA_FTIM3 0x0 214 #endif 215 216 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 217 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 218 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 219 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 220 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 221 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 222 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 223 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 224 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 225 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 226 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 227 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 228 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 229 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 230 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 231 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 232 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 233 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 234 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 235 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 236 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 237 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 238 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 239 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 240 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 241 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 242 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 243 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 244 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 245 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 246 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 247 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 248 249 /* 250 * Serial Port 251 */ 252 #define CONFIG_CONS_INDEX 1 253 #define CONFIG_SYS_NS16550 254 #define CONFIG_SYS_NS16550_SERIAL 255 #define CONFIG_SYS_NS16550_REG_SIZE 1 256 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 257 258 #define CONFIG_BAUDRATE 115200 259 260 /* 261 * I2C 262 */ 263 #define CONFIG_CMD_I2C 264 #define CONFIG_SYS_I2C 265 #define CONFIG_SYS_I2C_MXC 266 267 /* 268 * I2C bus multiplexer 269 */ 270 #define I2C_MUX_PCA_ADDR_PRI 0x77 271 #define I2C_MUX_CH_DEFAULT 0x8 272 273 /* 274 * MMC 275 */ 276 #define CONFIG_MMC 277 #define CONFIG_CMD_MMC 278 #define CONFIG_FSL_ESDHC 279 #define CONFIG_GENERIC_MMC 280 281 /* 282 * eTSEC 283 */ 284 #define CONFIG_TSEC_ENET 285 286 #ifdef CONFIG_TSEC_ENET 287 #define CONFIG_MII 288 #define CONFIG_MII_DEFAULT_TSEC 3 289 #define CONFIG_TSEC1 1 290 #define CONFIG_TSEC1_NAME "eTSEC1" 291 #define CONFIG_TSEC2 1 292 #define CONFIG_TSEC2_NAME "eTSEC2" 293 #define CONFIG_TSEC3 1 294 #define CONFIG_TSEC3_NAME "eTSEC3" 295 296 #define TSEC1_PHY_ADDR 1 297 #define TSEC2_PHY_ADDR 2 298 #define TSEC3_PHY_ADDR 3 299 300 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 301 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 302 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 303 304 #define TSEC1_PHYIDX 0 305 #define TSEC2_PHYIDX 0 306 #define TSEC3_PHYIDX 0 307 308 #define CONFIG_ETHPRIME "eTSEC1" 309 310 #define CONFIG_PHY_GIGE 311 #define CONFIG_PHYLIB 312 #define CONFIG_PHY_REALTEK 313 314 #define CONFIG_HAS_ETH0 315 #define CONFIG_HAS_ETH1 316 #define CONFIG_HAS_ETH2 317 318 #define CONFIG_FSL_SGMII_RISER 1 319 #define SGMII_RISER_PHY_OFFSET 0x1b 320 321 #ifdef CONFIG_FSL_SGMII_RISER 322 #define CONFIG_SYS_TBIPA_VALUE 8 323 #endif 324 325 #endif 326 #define CONFIG_CMD_PING 327 #define CONFIG_CMD_DHCP 328 #define CONFIG_CMD_MII 329 #define CONFIG_CMD_NET 330 331 #define CONFIG_CMDLINE_TAG 332 #define CONFIG_CMDLINE_EDITING 333 #define CONFIG_CMD_IMLS 334 335 #define CONFIG_HWCONFIG 336 #define HWCONFIG_BUFFER_SIZE 128 337 338 #define CONFIG_BOOTDELAY 3 339 340 #define CONFIG_SYS_QE_FW_ADDR 0x67f40000 341 342 #define CONFIG_EXTRA_ENV_SETTINGS \ 343 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 344 "fdt_high=0xcfffffff\0" \ 345 "initrd_high=0xcfffffff\0" \ 346 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 347 348 /* 349 * Miscellaneous configurable options 350 */ 351 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 352 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 353 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 354 #define CONFIG_SYS_PROMPT "=> " 355 #define CONFIG_AUTO_COMPLETE 356 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 357 #define CONFIG_SYS_PBSIZE \ 358 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 359 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 360 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 361 362 #define CONFIG_CMD_ENV_EXISTS 363 #define CONFIG_CMD_GREPENV 364 #define CONFIG_CMD_MEMINFO 365 #define CONFIG_CMD_MEMTEST 366 #define CONFIG_SYS_MEMTEST_START 0x80000000 367 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 368 369 #define CONFIG_SYS_LOAD_ADDR 0x82000000 370 371 /* 372 * Stack sizes 373 * The stack sizes are set up in start.S using the settings below 374 */ 375 #define CONFIG_STACKSIZE (30 * 1024) 376 377 #define CONFIG_SYS_INIT_SP_OFFSET \ 378 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 379 #define CONFIG_SYS_INIT_SP_ADDR \ 380 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 381 382 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 383 384 /* 385 * Environment 386 */ 387 #define CONFIG_ENV_OVERWRITE 388 389 #define CONFIG_ENV_IS_IN_FLASH 390 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 391 #define CONFIG_ENV_SIZE 0x2000 392 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 393 394 #define CONFIG_OF_LIBFDT 395 #define CONFIG_OF_BOARD_SETUP 396 #define CONFIG_CMD_BOOTZ 397 398 #define CONFIG_MISC_INIT_R 399 400 /* Hash command with SHA acceleration supported in hardware */ 401 #define CONFIG_CMD_HASH 402 #define CONFIG_SHA_HW_ACCEL 403 404 #ifdef CONFIG_SECURE_BOOT 405 #define CONFIG_CMD_BLOB 406 #endif 407 408 #endif 409