1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_LS102XA 11 12 #define CONFIG_ARMV7_PSCI_1_0 13 14 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 15 16 #define CONFIG_SYS_FSL_CLK 17 18 #define CONFIG_DISPLAY_CPUINFO 19 #define CONFIG_DISPLAY_BOARDINFO 20 21 #define CONFIG_SKIP_LOWLEVEL_INIT 22 #define CONFIG_BOARD_EARLY_INIT_F 23 24 #define CONFIG_DEEP_SLEEP 25 #if defined(CONFIG_DEEP_SLEEP) 26 #define CONFIG_SILENT_CONSOLE 27 #endif 28 29 /* 30 * Size of malloc() pool 31 */ 32 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 33 34 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 35 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 36 37 /* 38 * Generic Timer Definitions 39 */ 40 #define GENERIC_TIMER_CLK 12500000 41 42 #ifndef __ASSEMBLY__ 43 unsigned long get_board_sys_clk(void); 44 unsigned long get_board_ddr_clk(void); 45 #endif 46 47 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 48 #define CONFIG_SYS_CLK_FREQ 100000000 49 #define CONFIG_DDR_CLK_FREQ 100000000 50 #define CONFIG_QIXIS_I2C_ACCESS 51 #else 52 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 53 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 54 #endif 55 56 #ifdef CONFIG_RAMBOOT_PBL 57 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg 58 #endif 59 60 #ifdef CONFIG_SD_BOOT 61 #ifdef CONFIG_SD_BOOT_QSPI 62 #define CONFIG_SYS_FSL_PBL_RCW \ 63 board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg 64 #else 65 #define CONFIG_SYS_FSL_PBL_RCW \ 66 board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg 67 #endif 68 #define CONFIG_SPL_FRAMEWORK 69 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 70 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 71 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x600 72 73 #define CONFIG_SPL_TEXT_BASE 0x10000000 74 #define CONFIG_SPL_MAX_SIZE 0x1a000 75 #define CONFIG_SPL_STACK 0x1001d000 76 #define CONFIG_SPL_PAD_TO 0x1c000 77 #define CONFIG_SYS_TEXT_BASE 0x82000000 78 79 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 80 CONFIG_SYS_MONITOR_LEN) 81 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 82 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 83 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 84 #define CONFIG_SYS_MONITOR_LEN 0xc0000 85 #endif 86 87 #ifdef CONFIG_QSPI_BOOT 88 #define CONFIG_SYS_TEXT_BASE 0x40010000 89 #endif 90 91 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 92 #define CONFIG_SYS_NO_FLASH 93 #endif 94 95 #ifdef CONFIG_NAND_BOOT 96 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg 97 #define CONFIG_SPL_FRAMEWORK 98 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 99 100 #define CONFIG_SPL_TEXT_BASE 0x10000000 101 #define CONFIG_SPL_MAX_SIZE 0x1a000 102 #define CONFIG_SPL_STACK 0x1001d000 103 #define CONFIG_SPL_PAD_TO 0x1c000 104 #define CONFIG_SYS_TEXT_BASE 0x82000000 105 106 #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10) 107 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 108 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 109 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 110 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 111 112 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 113 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 114 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 115 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 116 #define CONFIG_SYS_MONITOR_LEN 0x80000 117 #endif 118 119 #ifndef CONFIG_SYS_TEXT_BASE 120 #define CONFIG_SYS_TEXT_BASE 0x60100000 121 #endif 122 123 #define CONFIG_NR_DRAM_BANKS 1 124 125 #define CONFIG_DDR_SPD 126 #define SPD_EEPROM_ADDRESS 0x51 127 #define CONFIG_SYS_SPD_BUS_NUM 0 128 129 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 130 #ifndef CONFIG_SYS_FSL_DDR4 131 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ 132 #define CONFIG_SYS_DDR_RAW_TIMING 133 #endif 134 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 135 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 136 137 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 138 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 139 140 #define CONFIG_DDR_ECC 141 #ifdef CONFIG_DDR_ECC 142 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 143 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 144 #endif 145 146 #define CONFIG_SYS_HAS_SERDES 147 148 #define CONFIG_FSL_CAAM /* Enable CAAM */ 149 150 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ 151 !defined(CONFIG_QSPI_BOOT) 152 #define CONFIG_U_QE 153 #endif 154 155 /* 156 * IFC Definitions 157 */ 158 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 159 #define CONFIG_FSL_IFC 160 #define CONFIG_SYS_FLASH_BASE 0x60000000 161 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 162 163 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 164 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 165 CSPR_PORT_SIZE_16 | \ 166 CSPR_MSEL_NOR | \ 167 CSPR_V) 168 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 169 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 170 + 0x8000000) | \ 171 CSPR_PORT_SIZE_16 | \ 172 CSPR_MSEL_NOR | \ 173 CSPR_V) 174 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 175 176 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 177 CSOR_NOR_TRHZ_80) 178 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 179 FTIM0_NOR_TEADC(0x5) | \ 180 FTIM0_NOR_TEAHC(0x5)) 181 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 182 FTIM1_NOR_TRAD_NOR(0x1a) | \ 183 FTIM1_NOR_TSEQRAD_NOR(0x13)) 184 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 185 FTIM2_NOR_TCH(0x4) | \ 186 FTIM2_NOR_TWPH(0xe) | \ 187 FTIM2_NOR_TWP(0x1c)) 188 #define CONFIG_SYS_NOR_FTIM3 0 189 190 #define CONFIG_FLASH_CFI_DRIVER 191 #define CONFIG_SYS_FLASH_CFI 192 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 193 #define CONFIG_SYS_FLASH_QUIET_TEST 194 #define CONFIG_FLASH_SHOW_PROGRESS 45 195 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 196 #define CONFIG_SYS_WRITE_SWAPPED_DATA 197 198 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 199 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 200 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 201 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 202 203 #define CONFIG_SYS_FLASH_EMPTY_INFO 204 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 205 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 206 207 /* 208 * NAND Flash Definitions 209 */ 210 #define CONFIG_NAND_FSL_IFC 211 212 #define CONFIG_SYS_NAND_BASE 0x7e800000 213 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 214 215 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 216 217 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 218 | CSPR_PORT_SIZE_8 \ 219 | CSPR_MSEL_NAND \ 220 | CSPR_V) 221 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 222 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 223 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 224 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 225 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 226 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 227 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 228 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 229 230 #define CONFIG_SYS_NAND_ONFI_DETECTION 231 232 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 233 FTIM0_NAND_TWP(0x18) | \ 234 FTIM0_NAND_TWCHT(0x7) | \ 235 FTIM0_NAND_TWH(0xa)) 236 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 237 FTIM1_NAND_TWBE(0x39) | \ 238 FTIM1_NAND_TRR(0xe) | \ 239 FTIM1_NAND_TRP(0x18)) 240 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 241 FTIM2_NAND_TREH(0xa) | \ 242 FTIM2_NAND_TWHRE(0x1e)) 243 #define CONFIG_SYS_NAND_FTIM3 0x0 244 245 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 246 #define CONFIG_SYS_MAX_NAND_DEVICE 1 247 #define CONFIG_CMD_NAND 248 249 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 250 #endif 251 252 /* 253 * QIXIS Definitions 254 */ 255 #define CONFIG_FSL_QIXIS 256 257 #ifdef CONFIG_FSL_QIXIS 258 #define QIXIS_BASE 0x7fb00000 259 #define QIXIS_BASE_PHYS QIXIS_BASE 260 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 261 #define QIXIS_LBMAP_SWITCH 6 262 #define QIXIS_LBMAP_MASK 0x0f 263 #define QIXIS_LBMAP_SHIFT 0 264 #define QIXIS_LBMAP_DFLTBANK 0x00 265 #define QIXIS_LBMAP_ALTBANK 0x04 266 #define QIXIS_PWR_CTL 0x21 267 #define QIXIS_PWR_CTL_POWEROFF 0x80 268 #define QIXIS_RST_CTL_RESET 0x44 269 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 270 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 271 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 272 273 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 274 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 275 CSPR_PORT_SIZE_8 | \ 276 CSPR_MSEL_GPCM | \ 277 CSPR_V) 278 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 279 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 280 CSOR_NOR_NOR_MODE_AVD_NOR | \ 281 CSOR_NOR_TRHZ_80) 282 283 /* 284 * QIXIS Timing parameters for IFC GPCM 285 */ 286 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \ 287 FTIM0_GPCM_TEADC(0xe) | \ 288 FTIM0_GPCM_TEAHC(0xe)) 289 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \ 290 FTIM1_GPCM_TRAD(0x1f)) 291 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \ 292 FTIM2_GPCM_TCH(0xe) | \ 293 FTIM2_GPCM_TWP(0xf0)) 294 #define CONFIG_SYS_FPGA_FTIM3 0x0 295 #endif 296 297 #if defined(CONFIG_NAND_BOOT) 298 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 299 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 300 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 301 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 302 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 303 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 304 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 305 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 306 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 307 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 308 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 309 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 310 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 311 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 312 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 313 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 314 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 315 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 316 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 317 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 318 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 319 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 320 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 321 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 322 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 323 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 324 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 325 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 326 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 327 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 328 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 329 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 330 #else 331 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 332 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 333 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 334 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 335 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 336 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 337 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 338 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 339 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 340 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 341 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 342 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 343 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 344 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 345 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 346 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 347 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 348 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 349 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 350 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 351 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 352 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 353 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 354 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 355 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 356 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 357 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 358 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 359 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 360 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 361 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 362 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 363 #endif 364 365 /* 366 * Serial Port 367 */ 368 #ifdef CONFIG_LPUART 369 #define CONFIG_LPUART_32B_REG 370 #else 371 #define CONFIG_CONS_INDEX 1 372 #define CONFIG_SYS_NS16550_SERIAL 373 #ifndef CONFIG_DM_SERIAL 374 #define CONFIG_SYS_NS16550_REG_SIZE 1 375 #endif 376 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 377 #endif 378 379 #define CONFIG_BAUDRATE 115200 380 381 /* 382 * I2C 383 */ 384 #define CONFIG_SYS_I2C 385 #define CONFIG_SYS_I2C_MXC 386 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 387 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 388 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 389 390 /* 391 * I2C bus multiplexer 392 */ 393 #define I2C_MUX_PCA_ADDR_PRI 0x77 394 #define I2C_MUX_CH_DEFAULT 0x8 395 #define I2C_MUX_CH_CH7301 0xC 396 397 /* 398 * MMC 399 */ 400 #define CONFIG_MMC 401 #define CONFIG_FSL_ESDHC 402 #define CONFIG_GENERIC_MMC 403 404 #define CONFIG_DOS_PARTITION 405 406 /* SPI */ 407 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 408 /* QSPI */ 409 #define QSPI0_AMBA_BASE 0x40000000 410 #define FSL_QSPI_FLASH_SIZE (1 << 24) 411 #define FSL_QSPI_FLASH_NUM 2 412 413 /* DSPI */ 414 415 /* DM SPI */ 416 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 417 #define CONFIG_DM_SPI_FLASH 418 #define CONFIG_SPI_FLASH_DATAFLASH 419 #endif 420 #endif 421 422 /* 423 * USB 424 */ 425 /* EHCI Support - disbaled by default */ 426 /*#define CONFIG_HAS_FSL_DR_USB*/ 427 428 #ifdef CONFIG_HAS_FSL_DR_USB 429 #define CONFIG_USB_EHCI 430 #define CONFIG_USB_EHCI_FSL 431 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 432 #endif 433 434 /*XHCI Support - enabled by default*/ 435 #define CONFIG_HAS_FSL_XHCI_USB 436 437 #ifdef CONFIG_HAS_FSL_XHCI_USB 438 #define CONFIG_USB_XHCI_FSL 439 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 440 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 441 #endif 442 443 /* 444 * Video 445 */ 446 #define CONFIG_FSL_DCU_FB 447 448 #ifdef CONFIG_FSL_DCU_FB 449 #define CONFIG_VIDEO 450 #define CONFIG_CMD_BMP 451 #define CONFIG_CFB_CONSOLE 452 #define CONFIG_VGA_AS_SINGLE_DEVICE 453 #define CONFIG_VIDEO_LOGO 454 #define CONFIG_VIDEO_BMP_LOGO 455 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 456 457 #define CONFIG_FSL_DIU_CH7301 458 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0 459 #define CONFIG_SYS_I2C_QIXIS_ADDR 0x66 460 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 461 #endif 462 463 /* 464 * eTSEC 465 */ 466 #define CONFIG_TSEC_ENET 467 468 #ifdef CONFIG_TSEC_ENET 469 #define CONFIG_MII 470 #define CONFIG_MII_DEFAULT_TSEC 3 471 #define CONFIG_TSEC1 1 472 #define CONFIG_TSEC1_NAME "eTSEC1" 473 #define CONFIG_TSEC2 1 474 #define CONFIG_TSEC2_NAME "eTSEC2" 475 #define CONFIG_TSEC3 1 476 #define CONFIG_TSEC3_NAME "eTSEC3" 477 478 #define TSEC1_PHY_ADDR 1 479 #define TSEC2_PHY_ADDR 2 480 #define TSEC3_PHY_ADDR 3 481 482 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 483 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 484 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 485 486 #define TSEC1_PHYIDX 0 487 #define TSEC2_PHYIDX 0 488 #define TSEC3_PHYIDX 0 489 490 #define CONFIG_ETHPRIME "eTSEC1" 491 492 #define CONFIG_PHY_GIGE 493 #define CONFIG_PHYLIB 494 #define CONFIG_PHY_REALTEK 495 496 #define CONFIG_HAS_ETH0 497 #define CONFIG_HAS_ETH1 498 #define CONFIG_HAS_ETH2 499 500 #define CONFIG_FSL_SGMII_RISER 1 501 #define SGMII_RISER_PHY_OFFSET 0x1b 502 503 #ifdef CONFIG_FSL_SGMII_RISER 504 #define CONFIG_SYS_TBIPA_VALUE 8 505 #endif 506 507 #endif 508 509 /* PCIe */ 510 #define CONFIG_PCI /* Enable PCI/PCIE */ 511 #define CONFIG_PCIE1 /* PCIE controller 1 */ 512 #define CONFIG_PCIE2 /* PCIE controller 2 */ 513 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 514 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" 515 516 #define CONFIG_SYS_PCI_64BIT 517 518 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 519 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ 520 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 521 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ 522 523 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 524 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 525 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ 526 527 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 528 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 529 #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ 530 531 #ifdef CONFIG_PCI 532 #define CONFIG_PCI_PNP 533 #define CONFIG_PCI_SCAN_SHOW 534 #define CONFIG_CMD_PCI 535 #endif 536 537 #define CONFIG_CMDLINE_TAG 538 #define CONFIG_CMDLINE_EDITING 539 540 #define CONFIG_ARMV7_NONSEC 541 #define CONFIG_ARMV7_VIRT 542 #define CONFIG_PEN_ADDR_BIG_ENDIAN 543 #define CONFIG_LAYERSCAPE_NS_ACCESS 544 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 545 #define CONFIG_TIMER_CLK_FREQ 12500000 546 547 #define CONFIG_HWCONFIG 548 #define HWCONFIG_BUFFER_SIZE 256 549 550 #define CONFIG_FSL_DEVICE_DISABLE 551 552 553 #define CONFIG_SYS_QE_FW_ADDR 0x600c0000 554 555 #ifdef CONFIG_LPUART 556 #define CONFIG_EXTRA_ENV_SETTINGS \ 557 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ 558 "fdt_high=0xffffffff\0" \ 559 "initrd_high=0xffffffff\0" \ 560 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 561 #else 562 #define CONFIG_EXTRA_ENV_SETTINGS \ 563 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 564 "fdt_high=0xffffffff\0" \ 565 "initrd_high=0xffffffff\0" \ 566 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 567 #endif 568 569 /* 570 * Miscellaneous configurable options 571 */ 572 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 573 #define CONFIG_AUTO_COMPLETE 574 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 575 #define CONFIG_SYS_PBSIZE \ 576 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 577 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 578 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 579 580 #define CONFIG_SYS_MEMTEST_START 0x80000000 581 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 582 583 #define CONFIG_SYS_LOAD_ADDR 0x82000000 584 585 #define CONFIG_LS102XA_STREAM_ID 586 587 /* 588 * Stack sizes 589 * The stack sizes are set up in start.S using the settings below 590 */ 591 #define CONFIG_STACKSIZE (30 * 1024) 592 593 #define CONFIG_SYS_INIT_SP_OFFSET \ 594 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 595 #define CONFIG_SYS_INIT_SP_ADDR \ 596 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 597 598 #ifdef CONFIG_SPL_BUILD 599 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 600 #else 601 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 602 #endif 603 604 /* 605 * Environment 606 */ 607 #define CONFIG_ENV_OVERWRITE 608 609 #if defined(CONFIG_SD_BOOT) 610 #define CONFIG_ENV_OFFSET 0x100000 611 #define CONFIG_ENV_IS_IN_MMC 612 #define CONFIG_SYS_MMC_ENV_DEV 0 613 #define CONFIG_ENV_SIZE 0x2000 614 #elif defined(CONFIG_QSPI_BOOT) 615 #define CONFIG_ENV_IS_IN_SPI_FLASH 616 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 617 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 618 #define CONFIG_ENV_SECT_SIZE 0x10000 619 #elif defined(CONFIG_NAND_BOOT) 620 #define CONFIG_ENV_IS_IN_NAND 621 #define CONFIG_ENV_SIZE 0x2000 622 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 623 #else 624 #define CONFIG_ENV_IS_IN_FLASH 625 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 626 #define CONFIG_ENV_SIZE 0x2000 627 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 628 #endif 629 630 #define CONFIG_MISC_INIT_R 631 632 /* Hash command with SHA acceleration supported in hardware */ 633 #ifdef CONFIG_FSL_CAAM 634 #define CONFIG_CMD_HASH 635 #define CONFIG_SHA_HW_ACCEL 636 #endif 637 638 #include <asm/fsl_secure_boot.h> 639 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 640 641 #endif 642