1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __CONFIG_H 7 #define __CONFIG_H 8 9 #define CONFIG_ARMV7_PSCI_1_0 10 11 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 12 13 #define CONFIG_SYS_FSL_CLK 14 15 #define CONFIG_SKIP_LOWLEVEL_INIT 16 17 #define CONFIG_DEEP_SLEEP 18 19 /* 20 * Size of malloc() pool 21 */ 22 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 23 24 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 25 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 26 27 #ifndef __ASSEMBLY__ 28 unsigned long get_board_sys_clk(void); 29 unsigned long get_board_ddr_clk(void); 30 #endif 31 32 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 33 #define CONFIG_SYS_CLK_FREQ 100000000 34 #define CONFIG_DDR_CLK_FREQ 100000000 35 #define CONFIG_QIXIS_I2C_ACCESS 36 #else 37 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 38 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 39 #endif 40 41 #ifdef CONFIG_RAMBOOT_PBL 42 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg 43 #endif 44 45 #ifdef CONFIG_SD_BOOT 46 #ifdef CONFIG_SD_BOOT_QSPI 47 #define CONFIG_SYS_FSL_PBL_RCW \ 48 board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg 49 #else 50 #define CONFIG_SYS_FSL_PBL_RCW \ 51 board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg 52 #endif 53 54 #define CONFIG_SPL_TEXT_BASE 0x10000000 55 #define CONFIG_SPL_MAX_SIZE 0x1a000 56 #define CONFIG_SPL_STACK 0x1001d000 57 #define CONFIG_SPL_PAD_TO 0x1c000 58 59 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 60 CONFIG_SYS_MONITOR_LEN) 61 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 62 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 63 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 64 #define CONFIG_SYS_MONITOR_LEN 0xc0000 65 #endif 66 67 #ifdef CONFIG_NAND_BOOT 68 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg 69 70 #define CONFIG_SPL_TEXT_BASE 0x10000000 71 #define CONFIG_SPL_MAX_SIZE 0x1a000 72 #define CONFIG_SPL_STACK 0x1001d000 73 #define CONFIG_SPL_PAD_TO 0x1c000 74 75 #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10) 76 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 77 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 78 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 79 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 80 81 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 82 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 83 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 84 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 85 #define CONFIG_SYS_MONITOR_LEN 0x80000 86 #endif 87 88 #define CONFIG_DDR_SPD 89 #define SPD_EEPROM_ADDRESS 0x51 90 #define CONFIG_SYS_SPD_BUS_NUM 0 91 92 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 93 #ifndef CONFIG_SYS_FSL_DDR4 94 #define CONFIG_SYS_DDR_RAW_TIMING 95 #endif 96 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 97 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 98 99 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 100 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 101 102 #define CONFIG_DDR_ECC 103 #ifdef CONFIG_DDR_ECC 104 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 105 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 106 #endif 107 108 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ 109 !defined(CONFIG_QSPI_BOOT) 110 #define CONFIG_U_QE 111 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 112 #endif 113 114 /* 115 * IFC Definitions 116 */ 117 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 118 #define CONFIG_FSL_IFC 119 #define CONFIG_SYS_FLASH_BASE 0x60000000 120 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 121 122 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 123 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 124 CSPR_PORT_SIZE_16 | \ 125 CSPR_MSEL_NOR | \ 126 CSPR_V) 127 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 128 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 129 + 0x8000000) | \ 130 CSPR_PORT_SIZE_16 | \ 131 CSPR_MSEL_NOR | \ 132 CSPR_V) 133 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 134 135 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 136 CSOR_NOR_TRHZ_80) 137 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 138 FTIM0_NOR_TEADC(0x5) | \ 139 FTIM0_NOR_TEAHC(0x5)) 140 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 141 FTIM1_NOR_TRAD_NOR(0x1a) | \ 142 FTIM1_NOR_TSEQRAD_NOR(0x13)) 143 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 144 FTIM2_NOR_TCH(0x4) | \ 145 FTIM2_NOR_TWPH(0xe) | \ 146 FTIM2_NOR_TWP(0x1c)) 147 #define CONFIG_SYS_NOR_FTIM3 0 148 149 #define CONFIG_FLASH_CFI_DRIVER 150 #define CONFIG_SYS_FLASH_CFI 151 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 152 #define CONFIG_SYS_FLASH_QUIET_TEST 153 #define CONFIG_FLASH_SHOW_PROGRESS 45 154 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 155 #define CONFIG_SYS_WRITE_SWAPPED_DATA 156 157 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 158 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 159 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 160 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 161 162 #define CONFIG_SYS_FLASH_EMPTY_INFO 163 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 164 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 165 166 /* 167 * NAND Flash Definitions 168 */ 169 #define CONFIG_NAND_FSL_IFC 170 171 #define CONFIG_SYS_NAND_BASE 0x7e800000 172 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 173 174 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 175 176 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 177 | CSPR_PORT_SIZE_8 \ 178 | CSPR_MSEL_NAND \ 179 | CSPR_V) 180 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 181 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 182 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 183 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 184 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 185 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 186 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 187 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 188 189 #define CONFIG_SYS_NAND_ONFI_DETECTION 190 191 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 192 FTIM0_NAND_TWP(0x18) | \ 193 FTIM0_NAND_TWCHT(0x7) | \ 194 FTIM0_NAND_TWH(0xa)) 195 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 196 FTIM1_NAND_TWBE(0x39) | \ 197 FTIM1_NAND_TRR(0xe) | \ 198 FTIM1_NAND_TRP(0x18)) 199 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 200 FTIM2_NAND_TREH(0xa) | \ 201 FTIM2_NAND_TWHRE(0x1e)) 202 #define CONFIG_SYS_NAND_FTIM3 0x0 203 204 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 205 #define CONFIG_SYS_MAX_NAND_DEVICE 1 206 207 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 208 #endif 209 210 /* 211 * QIXIS Definitions 212 */ 213 #define CONFIG_FSL_QIXIS 214 215 #ifdef CONFIG_FSL_QIXIS 216 #define QIXIS_BASE 0x7fb00000 217 #define QIXIS_BASE_PHYS QIXIS_BASE 218 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 219 #define QIXIS_LBMAP_SWITCH 6 220 #define QIXIS_LBMAP_MASK 0x0f 221 #define QIXIS_LBMAP_SHIFT 0 222 #define QIXIS_LBMAP_DFLTBANK 0x00 223 #define QIXIS_LBMAP_ALTBANK 0x04 224 #define QIXIS_PWR_CTL 0x21 225 #define QIXIS_PWR_CTL_POWEROFF 0x80 226 #define QIXIS_RST_CTL_RESET 0x44 227 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 228 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 229 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 230 #define QIXIS_CTL_SYS 0x5 231 #define QIXIS_CTL_SYS_EVTSW_MASK 0x0c 232 #define QIXIS_CTL_SYS_EVTSW_IRQ 0x04 233 #define QIXIS_RST_FORCE_3 0x45 234 #define QIXIS_RST_FORCE_3_PCIESLOT1 0x80 235 #define QIXIS_PWR_CTL2 0x21 236 #define QIXIS_PWR_CTL2_PCTL 0x2 237 238 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 239 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 240 CSPR_PORT_SIZE_8 | \ 241 CSPR_MSEL_GPCM | \ 242 CSPR_V) 243 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 244 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 245 CSOR_NOR_NOR_MODE_AVD_NOR | \ 246 CSOR_NOR_TRHZ_80) 247 248 /* 249 * QIXIS Timing parameters for IFC GPCM 250 */ 251 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \ 252 FTIM0_GPCM_TEADC(0xe) | \ 253 FTIM0_GPCM_TEAHC(0xe)) 254 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \ 255 FTIM1_GPCM_TRAD(0x1f)) 256 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \ 257 FTIM2_GPCM_TCH(0xe) | \ 258 FTIM2_GPCM_TWP(0xf0)) 259 #define CONFIG_SYS_FPGA_FTIM3 0x0 260 #endif 261 262 #if defined(CONFIG_NAND_BOOT) 263 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 264 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 265 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 266 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 267 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 268 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 269 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 270 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 271 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 272 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 273 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 274 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 275 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 276 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 277 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 278 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 279 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 280 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 281 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 282 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 283 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 284 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 285 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 286 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 287 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 288 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 289 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 290 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 291 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 292 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 293 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 294 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 295 #else 296 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 297 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 298 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 299 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 300 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 301 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 302 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 303 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 304 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 305 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 306 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 307 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 308 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 309 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 310 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 311 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 312 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 313 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 314 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 315 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 316 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 317 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 318 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 319 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 320 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 321 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 322 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 323 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 324 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 325 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 326 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 327 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 328 #endif 329 330 /* 331 * Serial Port 332 */ 333 #ifdef CONFIG_LPUART 334 #define CONFIG_LPUART_32B_REG 335 #else 336 #define CONFIG_SYS_NS16550_SERIAL 337 #ifndef CONFIG_DM_SERIAL 338 #define CONFIG_SYS_NS16550_REG_SIZE 1 339 #endif 340 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 341 #endif 342 343 /* 344 * I2C 345 */ 346 #define CONFIG_SYS_I2C 347 #define CONFIG_SYS_I2C_MXC 348 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 349 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 350 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 351 352 /* EEPROM */ 353 #define CONFIG_ID_EEPROM 354 #define CONFIG_SYS_I2C_EEPROM_NXID 355 #define CONFIG_SYS_EEPROM_BUS_NUM 0 356 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 357 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 358 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 359 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 360 361 /* 362 * I2C bus multiplexer 363 */ 364 #define I2C_MUX_PCA_ADDR_PRI 0x77 365 #define I2C_MUX_CH_DEFAULT 0x8 366 #define I2C_MUX_CH_CH7301 0xC 367 368 /* 369 * MMC 370 */ 371 372 /* SPI */ 373 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 374 /* QSPI */ 375 #define QSPI0_AMBA_BASE 0x40000000 376 #define FSL_QSPI_FLASH_SIZE (1 << 24) 377 #define FSL_QSPI_FLASH_NUM 2 378 379 /* DSPI */ 380 381 /* DM SPI */ 382 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 383 #define CONFIG_DM_SPI_FLASH 384 #define CONFIG_SPI_FLASH_DATAFLASH 385 #endif 386 #endif 387 388 /* 389 * Video 390 */ 391 #ifdef CONFIG_VIDEO_FSL_DCU_FB 392 #define CONFIG_VIDEO_LOGO 393 #define CONFIG_VIDEO_BMP_LOGO 394 395 #define CONFIG_FSL_DIU_CH7301 396 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0 397 #define CONFIG_SYS_I2C_QIXIS_ADDR 0x66 398 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 399 #endif 400 401 /* 402 * eTSEC 403 */ 404 405 #ifdef CONFIG_TSEC_ENET 406 #define CONFIG_MII_DEFAULT_TSEC 3 407 #define CONFIG_TSEC1 1 408 #define CONFIG_TSEC1_NAME "eTSEC1" 409 #define CONFIG_TSEC2 1 410 #define CONFIG_TSEC2_NAME "eTSEC2" 411 #define CONFIG_TSEC3 1 412 #define CONFIG_TSEC3_NAME "eTSEC3" 413 414 #define TSEC1_PHY_ADDR 1 415 #define TSEC2_PHY_ADDR 2 416 #define TSEC3_PHY_ADDR 3 417 418 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 419 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 420 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 421 422 #define TSEC1_PHYIDX 0 423 #define TSEC2_PHYIDX 0 424 #define TSEC3_PHYIDX 0 425 426 #define CONFIG_ETHPRIME "eTSEC1" 427 428 #define CONFIG_PHY_REALTEK 429 430 #define CONFIG_HAS_ETH0 431 #define CONFIG_HAS_ETH1 432 #define CONFIG_HAS_ETH2 433 434 #define CONFIG_FSL_SGMII_RISER 1 435 #define SGMII_RISER_PHY_OFFSET 0x1b 436 437 #ifdef CONFIG_FSL_SGMII_RISER 438 #define CONFIG_SYS_TBIPA_VALUE 8 439 #endif 440 441 #endif 442 443 /* PCIe */ 444 #define CONFIG_PCIE1 /* PCIE controller 1 */ 445 #define CONFIG_PCIE2 /* PCIE controller 2 */ 446 447 #ifdef CONFIG_PCI 448 #define CONFIG_PCI_SCAN_SHOW 449 #endif 450 451 #define CONFIG_CMDLINE_TAG 452 453 #define CONFIG_PEN_ADDR_BIG_ENDIAN 454 #define CONFIG_LAYERSCAPE_NS_ACCESS 455 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 456 #define COUNTER_FREQUENCY 12500000 457 458 #define CONFIG_HWCONFIG 459 #define HWCONFIG_BUFFER_SIZE 256 460 461 #define CONFIG_FSL_DEVICE_DISABLE 462 463 464 #define CONFIG_SYS_QE_FW_ADDR 0x60940000 465 466 #ifdef CONFIG_LPUART 467 #define CONFIG_EXTRA_ENV_SETTINGS \ 468 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ 469 "fdt_high=0xffffffff\0" \ 470 "initrd_high=0xffffffff\0" \ 471 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 472 #else 473 #define CONFIG_EXTRA_ENV_SETTINGS \ 474 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 475 "fdt_high=0xffffffff\0" \ 476 "initrd_high=0xffffffff\0" \ 477 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 478 #endif 479 480 /* 481 * Miscellaneous configurable options 482 */ 483 484 #define CONFIG_SYS_MEMTEST_START 0x80000000 485 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 486 487 #define CONFIG_SYS_LOAD_ADDR 0x82000000 488 489 #define CONFIG_LS102XA_STREAM_ID 490 491 #define CONFIG_SYS_INIT_SP_OFFSET \ 492 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 493 #define CONFIG_SYS_INIT_SP_ADDR \ 494 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 495 496 #ifdef CONFIG_SPL_BUILD 497 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 498 #else 499 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 500 #endif 501 502 /* 503 * Environment 504 */ 505 #define CONFIG_ENV_OVERWRITE 506 507 #if defined(CONFIG_SD_BOOT) 508 #define CONFIG_ENV_OFFSET 0x300000 509 #define CONFIG_SYS_MMC_ENV_DEV 0 510 #define CONFIG_ENV_SIZE 0x2000 511 #elif defined(CONFIG_QSPI_BOOT) 512 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 513 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ 514 #define CONFIG_ENV_SECT_SIZE 0x10000 515 #elif defined(CONFIG_NAND_BOOT) 516 #define CONFIG_ENV_SIZE 0x2000 517 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 518 #else 519 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 520 #define CONFIG_ENV_SIZE 0x2000 521 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 522 #endif 523 524 #include <asm/fsl_secure_boot.h> 525 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 526 527 #endif 528