1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_LS102XA 11 12 #define CONFIG_ARMV7_PSCI_1_0 13 14 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 15 16 #define CONFIG_SYS_FSL_CLK 17 18 #define CONFIG_SKIP_LOWLEVEL_INIT 19 #define CONFIG_BOARD_EARLY_INIT_F 20 21 #define CONFIG_DEEP_SLEEP 22 23 /* 24 * Size of malloc() pool 25 */ 26 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 27 28 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 29 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 30 31 /* 32 * Generic Timer Definitions 33 */ 34 #define GENERIC_TIMER_CLK 12500000 35 36 #ifndef __ASSEMBLY__ 37 unsigned long get_board_sys_clk(void); 38 unsigned long get_board_ddr_clk(void); 39 #endif 40 41 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 42 #define CONFIG_SYS_CLK_FREQ 100000000 43 #define CONFIG_DDR_CLK_FREQ 100000000 44 #define CONFIG_QIXIS_I2C_ACCESS 45 #else 46 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 47 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 48 #endif 49 50 #ifdef CONFIG_RAMBOOT_PBL 51 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg 52 #endif 53 54 #ifdef CONFIG_SD_BOOT 55 #ifdef CONFIG_SD_BOOT_QSPI 56 #define CONFIG_SYS_FSL_PBL_RCW \ 57 board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg 58 #else 59 #define CONFIG_SYS_FSL_PBL_RCW \ 60 board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg 61 #endif 62 #define CONFIG_SPL_FRAMEWORK 63 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 64 65 #define CONFIG_SPL_TEXT_BASE 0x10000000 66 #define CONFIG_SPL_MAX_SIZE 0x1a000 67 #define CONFIG_SPL_STACK 0x1001d000 68 #define CONFIG_SPL_PAD_TO 0x1c000 69 #define CONFIG_SYS_TEXT_BASE 0x82000000 70 71 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 72 CONFIG_SYS_MONITOR_LEN) 73 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 74 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 75 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 76 #define CONFIG_SYS_MONITOR_LEN 0xc0000 77 #endif 78 79 #ifdef CONFIG_QSPI_BOOT 80 #define CONFIG_SYS_TEXT_BASE 0x40010000 81 #endif 82 83 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 84 #define CONFIG_SYS_NO_FLASH 85 #endif 86 87 #ifdef CONFIG_NAND_BOOT 88 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg 89 #define CONFIG_SPL_FRAMEWORK 90 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 91 92 #define CONFIG_SPL_TEXT_BASE 0x10000000 93 #define CONFIG_SPL_MAX_SIZE 0x1a000 94 #define CONFIG_SPL_STACK 0x1001d000 95 #define CONFIG_SPL_PAD_TO 0x1c000 96 #define CONFIG_SYS_TEXT_BASE 0x82000000 97 98 #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10) 99 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 100 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 101 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 102 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 103 104 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 105 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 106 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 107 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 108 #define CONFIG_SYS_MONITOR_LEN 0x80000 109 #endif 110 111 #ifndef CONFIG_SYS_TEXT_BASE 112 #define CONFIG_SYS_TEXT_BASE 0x60100000 113 #endif 114 115 #define CONFIG_NR_DRAM_BANKS 1 116 117 #define CONFIG_DDR_SPD 118 #define SPD_EEPROM_ADDRESS 0x51 119 #define CONFIG_SYS_SPD_BUS_NUM 0 120 121 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 122 #ifndef CONFIG_SYS_FSL_DDR4 123 #define CONFIG_SYS_DDR_RAW_TIMING 124 #endif 125 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 126 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 127 128 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 129 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 130 131 #define CONFIG_DDR_ECC 132 #ifdef CONFIG_DDR_ECC 133 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 134 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 135 #endif 136 137 #define CONFIG_FSL_CAAM /* Enable CAAM */ 138 139 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ 140 !defined(CONFIG_QSPI_BOOT) 141 #define CONFIG_U_QE 142 #endif 143 144 /* 145 * IFC Definitions 146 */ 147 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 148 #define CONFIG_FSL_IFC 149 #define CONFIG_SYS_FLASH_BASE 0x60000000 150 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 151 152 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 153 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 154 CSPR_PORT_SIZE_16 | \ 155 CSPR_MSEL_NOR | \ 156 CSPR_V) 157 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 158 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 159 + 0x8000000) | \ 160 CSPR_PORT_SIZE_16 | \ 161 CSPR_MSEL_NOR | \ 162 CSPR_V) 163 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 164 165 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 166 CSOR_NOR_TRHZ_80) 167 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 168 FTIM0_NOR_TEADC(0x5) | \ 169 FTIM0_NOR_TEAHC(0x5)) 170 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 171 FTIM1_NOR_TRAD_NOR(0x1a) | \ 172 FTIM1_NOR_TSEQRAD_NOR(0x13)) 173 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 174 FTIM2_NOR_TCH(0x4) | \ 175 FTIM2_NOR_TWPH(0xe) | \ 176 FTIM2_NOR_TWP(0x1c)) 177 #define CONFIG_SYS_NOR_FTIM3 0 178 179 #define CONFIG_FLASH_CFI_DRIVER 180 #define CONFIG_SYS_FLASH_CFI 181 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 182 #define CONFIG_SYS_FLASH_QUIET_TEST 183 #define CONFIG_FLASH_SHOW_PROGRESS 45 184 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 185 #define CONFIG_SYS_WRITE_SWAPPED_DATA 186 187 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 188 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 189 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 190 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 191 192 #define CONFIG_SYS_FLASH_EMPTY_INFO 193 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 194 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 195 196 /* 197 * NAND Flash Definitions 198 */ 199 #define CONFIG_NAND_FSL_IFC 200 201 #define CONFIG_SYS_NAND_BASE 0x7e800000 202 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 203 204 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 205 206 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 207 | CSPR_PORT_SIZE_8 \ 208 | CSPR_MSEL_NAND \ 209 | CSPR_V) 210 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 211 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 212 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 213 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 214 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 215 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 216 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 217 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 218 219 #define CONFIG_SYS_NAND_ONFI_DETECTION 220 221 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 222 FTIM0_NAND_TWP(0x18) | \ 223 FTIM0_NAND_TWCHT(0x7) | \ 224 FTIM0_NAND_TWH(0xa)) 225 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 226 FTIM1_NAND_TWBE(0x39) | \ 227 FTIM1_NAND_TRR(0xe) | \ 228 FTIM1_NAND_TRP(0x18)) 229 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 230 FTIM2_NAND_TREH(0xa) | \ 231 FTIM2_NAND_TWHRE(0x1e)) 232 #define CONFIG_SYS_NAND_FTIM3 0x0 233 234 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 235 #define CONFIG_SYS_MAX_NAND_DEVICE 1 236 #define CONFIG_CMD_NAND 237 238 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 239 #endif 240 241 /* 242 * QIXIS Definitions 243 */ 244 #define CONFIG_FSL_QIXIS 245 246 #ifdef CONFIG_FSL_QIXIS 247 #define QIXIS_BASE 0x7fb00000 248 #define QIXIS_BASE_PHYS QIXIS_BASE 249 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 250 #define QIXIS_LBMAP_SWITCH 6 251 #define QIXIS_LBMAP_MASK 0x0f 252 #define QIXIS_LBMAP_SHIFT 0 253 #define QIXIS_LBMAP_DFLTBANK 0x00 254 #define QIXIS_LBMAP_ALTBANK 0x04 255 #define QIXIS_PWR_CTL 0x21 256 #define QIXIS_PWR_CTL_POWEROFF 0x80 257 #define QIXIS_RST_CTL_RESET 0x44 258 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 259 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 260 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 261 #define QIXIS_CTL_SYS 0x5 262 #define QIXIS_CTL_SYS_EVTSW_MASK 0x0c 263 #define QIXIS_CTL_SYS_EVTSW_IRQ 0x04 264 #define QIXIS_RST_FORCE_3 0x45 265 #define QIXIS_RST_FORCE_3_PCIESLOT1 0x80 266 #define QIXIS_PWR_CTL2 0x21 267 #define QIXIS_PWR_CTL2_PCTL 0x2 268 269 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 270 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 271 CSPR_PORT_SIZE_8 | \ 272 CSPR_MSEL_GPCM | \ 273 CSPR_V) 274 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 275 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 276 CSOR_NOR_NOR_MODE_AVD_NOR | \ 277 CSOR_NOR_TRHZ_80) 278 279 /* 280 * QIXIS Timing parameters for IFC GPCM 281 */ 282 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \ 283 FTIM0_GPCM_TEADC(0xe) | \ 284 FTIM0_GPCM_TEAHC(0xe)) 285 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \ 286 FTIM1_GPCM_TRAD(0x1f)) 287 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \ 288 FTIM2_GPCM_TCH(0xe) | \ 289 FTIM2_GPCM_TWP(0xf0)) 290 #define CONFIG_SYS_FPGA_FTIM3 0x0 291 #endif 292 293 #if defined(CONFIG_NAND_BOOT) 294 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 295 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 296 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 297 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 298 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 299 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 300 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 301 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 302 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 303 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 304 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 305 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 306 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 307 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 308 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 309 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 310 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 311 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 312 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 313 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 314 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 315 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 316 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 317 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 318 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 319 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 320 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 321 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 322 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 323 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 324 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 325 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 326 #else 327 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 328 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 329 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 330 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 331 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 332 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 333 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 334 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 335 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 336 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 337 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 338 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 339 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 340 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 341 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 342 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 343 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 344 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 345 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 346 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 347 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 348 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 349 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 350 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 351 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 352 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 353 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 354 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 355 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 356 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 357 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 358 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 359 #endif 360 361 /* 362 * Serial Port 363 */ 364 #ifdef CONFIG_LPUART 365 #define CONFIG_LPUART_32B_REG 366 #else 367 #define CONFIG_CONS_INDEX 1 368 #define CONFIG_SYS_NS16550_SERIAL 369 #ifndef CONFIG_DM_SERIAL 370 #define CONFIG_SYS_NS16550_REG_SIZE 1 371 #endif 372 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 373 #endif 374 375 #define CONFIG_BAUDRATE 115200 376 377 /* 378 * I2C 379 */ 380 #define CONFIG_SYS_I2C 381 #define CONFIG_SYS_I2C_MXC 382 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 383 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 384 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 385 386 /* 387 * I2C bus multiplexer 388 */ 389 #define I2C_MUX_PCA_ADDR_PRI 0x77 390 #define I2C_MUX_CH_DEFAULT 0x8 391 #define I2C_MUX_CH_CH7301 0xC 392 393 /* 394 * MMC 395 */ 396 #define CONFIG_MMC 397 #define CONFIG_FSL_ESDHC 398 #define CONFIG_GENERIC_MMC 399 400 #define CONFIG_DOS_PARTITION 401 402 /* SPI */ 403 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 404 /* QSPI */ 405 #define QSPI0_AMBA_BASE 0x40000000 406 #define FSL_QSPI_FLASH_SIZE (1 << 24) 407 #define FSL_QSPI_FLASH_NUM 2 408 409 /* DSPI */ 410 411 /* DM SPI */ 412 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 413 #define CONFIG_DM_SPI_FLASH 414 #define CONFIG_SPI_FLASH_DATAFLASH 415 #endif 416 #endif 417 418 /* 419 * USB 420 */ 421 /* EHCI Support - disbaled by default */ 422 /*#define CONFIG_HAS_FSL_DR_USB*/ 423 424 #ifdef CONFIG_HAS_FSL_DR_USB 425 #define CONFIG_USB_EHCI 426 #define CONFIG_USB_EHCI_FSL 427 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 428 #endif 429 430 /*XHCI Support - enabled by default*/ 431 #define CONFIG_HAS_FSL_XHCI_USB 432 433 #ifdef CONFIG_HAS_FSL_XHCI_USB 434 #define CONFIG_USB_XHCI_FSL 435 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 436 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 437 #endif 438 439 /* 440 * Video 441 */ 442 #define CONFIG_FSL_DCU_FB 443 444 #ifdef CONFIG_FSL_DCU_FB 445 #define CONFIG_CMD_BMP 446 #define CONFIG_VIDEO_LOGO 447 #define CONFIG_VIDEO_BMP_LOGO 448 449 #define CONFIG_FSL_DIU_CH7301 450 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0 451 #define CONFIG_SYS_I2C_QIXIS_ADDR 0x66 452 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 453 #endif 454 455 /* 456 * eTSEC 457 */ 458 #define CONFIG_TSEC_ENET 459 460 #ifdef CONFIG_TSEC_ENET 461 #define CONFIG_MII 462 #define CONFIG_MII_DEFAULT_TSEC 3 463 #define CONFIG_TSEC1 1 464 #define CONFIG_TSEC1_NAME "eTSEC1" 465 #define CONFIG_TSEC2 1 466 #define CONFIG_TSEC2_NAME "eTSEC2" 467 #define CONFIG_TSEC3 1 468 #define CONFIG_TSEC3_NAME "eTSEC3" 469 470 #define TSEC1_PHY_ADDR 1 471 #define TSEC2_PHY_ADDR 2 472 #define TSEC3_PHY_ADDR 3 473 474 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 475 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 476 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 477 478 #define TSEC1_PHYIDX 0 479 #define TSEC2_PHYIDX 0 480 #define TSEC3_PHYIDX 0 481 482 #define CONFIG_ETHPRIME "eTSEC1" 483 484 #define CONFIG_PHY_GIGE 485 #define CONFIG_PHYLIB 486 #define CONFIG_PHY_REALTEK 487 488 #define CONFIG_HAS_ETH0 489 #define CONFIG_HAS_ETH1 490 #define CONFIG_HAS_ETH2 491 492 #define CONFIG_FSL_SGMII_RISER 1 493 #define SGMII_RISER_PHY_OFFSET 0x1b 494 495 #ifdef CONFIG_FSL_SGMII_RISER 496 #define CONFIG_SYS_TBIPA_VALUE 8 497 #endif 498 499 #endif 500 501 /* PCIe */ 502 #define CONFIG_PCIE1 /* PCIE controller 1 */ 503 #define CONFIG_PCIE2 /* PCIE controller 2 */ 504 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 505 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" 506 507 #define CONFIG_SYS_PCI_64BIT 508 509 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 510 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ 511 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 512 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ 513 514 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 515 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 516 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ 517 518 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 519 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 520 #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ 521 522 #ifdef CONFIG_PCI 523 #define CONFIG_PCI_SCAN_SHOW 524 #define CONFIG_CMD_PCI 525 #endif 526 527 #define CONFIG_CMDLINE_TAG 528 #define CONFIG_CMDLINE_EDITING 529 530 #define CONFIG_PEN_ADDR_BIG_ENDIAN 531 #define CONFIG_LAYERSCAPE_NS_ACCESS 532 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 533 #define CONFIG_TIMER_CLK_FREQ 12500000 534 535 #define CONFIG_HWCONFIG 536 #define HWCONFIG_BUFFER_SIZE 256 537 538 #define CONFIG_FSL_DEVICE_DISABLE 539 540 541 #define CONFIG_SYS_QE_FW_ADDR 0x600c0000 542 543 #ifdef CONFIG_LPUART 544 #define CONFIG_EXTRA_ENV_SETTINGS \ 545 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ 546 "fdt_high=0xffffffff\0" \ 547 "initrd_high=0xffffffff\0" \ 548 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 549 #else 550 #define CONFIG_EXTRA_ENV_SETTINGS \ 551 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 552 "fdt_high=0xffffffff\0" \ 553 "initrd_high=0xffffffff\0" \ 554 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 555 #endif 556 557 /* 558 * Miscellaneous configurable options 559 */ 560 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 561 #define CONFIG_AUTO_COMPLETE 562 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 563 #define CONFIG_SYS_PBSIZE \ 564 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 565 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 566 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 567 568 #define CONFIG_SYS_MEMTEST_START 0x80000000 569 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 570 571 #define CONFIG_SYS_LOAD_ADDR 0x82000000 572 573 #define CONFIG_LS102XA_STREAM_ID 574 575 /* 576 * Stack sizes 577 * The stack sizes are set up in start.S using the settings below 578 */ 579 #define CONFIG_STACKSIZE (30 * 1024) 580 581 #define CONFIG_SYS_INIT_SP_OFFSET \ 582 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 583 #define CONFIG_SYS_INIT_SP_ADDR \ 584 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 585 586 #ifdef CONFIG_SPL_BUILD 587 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 588 #else 589 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 590 #endif 591 592 /* 593 * Environment 594 */ 595 #define CONFIG_ENV_OVERWRITE 596 597 #if defined(CONFIG_SD_BOOT) 598 #define CONFIG_ENV_OFFSET 0x100000 599 #define CONFIG_ENV_IS_IN_MMC 600 #define CONFIG_SYS_MMC_ENV_DEV 0 601 #define CONFIG_ENV_SIZE 0x2000 602 #elif defined(CONFIG_QSPI_BOOT) 603 #define CONFIG_ENV_IS_IN_SPI_FLASH 604 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 605 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 606 #define CONFIG_ENV_SECT_SIZE 0x10000 607 #elif defined(CONFIG_NAND_BOOT) 608 #define CONFIG_ENV_IS_IN_NAND 609 #define CONFIG_ENV_SIZE 0x2000 610 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 611 #else 612 #define CONFIG_ENV_IS_IN_FLASH 613 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 614 #define CONFIG_ENV_SIZE 0x2000 615 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 616 #endif 617 618 #define CONFIG_MISC_INIT_R 619 620 /* Hash command with SHA acceleration supported in hardware */ 621 #ifdef CONFIG_FSL_CAAM 622 #define CONFIG_CMD_HASH 623 #define CONFIG_SHA_HW_ACCEL 624 #endif 625 626 #include <asm/fsl_secure_boot.h> 627 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 628 629 #endif 630