1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_ARMV7_PSCI_1_0 11 12 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 13 14 #define CONFIG_SYS_FSL_CLK 15 16 #define CONFIG_SKIP_LOWLEVEL_INIT 17 18 #define CONFIG_DEEP_SLEEP 19 20 /* 21 * Size of malloc() pool 22 */ 23 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 24 25 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 26 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 27 28 #ifndef __ASSEMBLY__ 29 unsigned long get_board_sys_clk(void); 30 unsigned long get_board_ddr_clk(void); 31 #endif 32 33 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 34 #define CONFIG_SYS_CLK_FREQ 100000000 35 #define CONFIG_DDR_CLK_FREQ 100000000 36 #define CONFIG_QIXIS_I2C_ACCESS 37 #else 38 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 39 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 40 #endif 41 42 #ifdef CONFIG_RAMBOOT_PBL 43 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg 44 #endif 45 46 #ifdef CONFIG_SD_BOOT 47 #ifdef CONFIG_SD_BOOT_QSPI 48 #define CONFIG_SYS_FSL_PBL_RCW \ 49 board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg 50 #else 51 #define CONFIG_SYS_FSL_PBL_RCW \ 52 board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg 53 #endif 54 55 #define CONFIG_SPL_TEXT_BASE 0x10000000 56 #define CONFIG_SPL_MAX_SIZE 0x1a000 57 #define CONFIG_SPL_STACK 0x1001d000 58 #define CONFIG_SPL_PAD_TO 0x1c000 59 60 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 61 CONFIG_SYS_MONITOR_LEN) 62 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 63 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 64 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 65 #define CONFIG_SYS_MONITOR_LEN 0xc0000 66 #endif 67 68 #ifdef CONFIG_NAND_BOOT 69 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg 70 71 #define CONFIG_SPL_TEXT_BASE 0x10000000 72 #define CONFIG_SPL_MAX_SIZE 0x1a000 73 #define CONFIG_SPL_STACK 0x1001d000 74 #define CONFIG_SPL_PAD_TO 0x1c000 75 76 #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10) 77 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 78 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 79 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 80 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 81 82 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 83 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 84 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 85 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 86 #define CONFIG_SYS_MONITOR_LEN 0x80000 87 #endif 88 89 #define CONFIG_NR_DRAM_BANKS 1 90 91 #define CONFIG_DDR_SPD 92 #define SPD_EEPROM_ADDRESS 0x51 93 #define CONFIG_SYS_SPD_BUS_NUM 0 94 95 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 96 #ifndef CONFIG_SYS_FSL_DDR4 97 #define CONFIG_SYS_DDR_RAW_TIMING 98 #endif 99 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 100 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 101 102 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 103 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 104 105 #define CONFIG_DDR_ECC 106 #ifdef CONFIG_DDR_ECC 107 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 108 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 109 #endif 110 111 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ 112 !defined(CONFIG_QSPI_BOOT) 113 #define CONFIG_U_QE 114 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 115 #endif 116 117 /* 118 * IFC Definitions 119 */ 120 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 121 #define CONFIG_FSL_IFC 122 #define CONFIG_SYS_FLASH_BASE 0x60000000 123 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 124 125 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 126 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 127 CSPR_PORT_SIZE_16 | \ 128 CSPR_MSEL_NOR | \ 129 CSPR_V) 130 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 131 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 132 + 0x8000000) | \ 133 CSPR_PORT_SIZE_16 | \ 134 CSPR_MSEL_NOR | \ 135 CSPR_V) 136 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 137 138 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 139 CSOR_NOR_TRHZ_80) 140 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 141 FTIM0_NOR_TEADC(0x5) | \ 142 FTIM0_NOR_TEAHC(0x5)) 143 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 144 FTIM1_NOR_TRAD_NOR(0x1a) | \ 145 FTIM1_NOR_TSEQRAD_NOR(0x13)) 146 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 147 FTIM2_NOR_TCH(0x4) | \ 148 FTIM2_NOR_TWPH(0xe) | \ 149 FTIM2_NOR_TWP(0x1c)) 150 #define CONFIG_SYS_NOR_FTIM3 0 151 152 #define CONFIG_FLASH_CFI_DRIVER 153 #define CONFIG_SYS_FLASH_CFI 154 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 155 #define CONFIG_SYS_FLASH_QUIET_TEST 156 #define CONFIG_FLASH_SHOW_PROGRESS 45 157 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 158 #define CONFIG_SYS_WRITE_SWAPPED_DATA 159 160 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 161 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 162 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 163 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 164 165 #define CONFIG_SYS_FLASH_EMPTY_INFO 166 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 167 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 168 169 /* 170 * NAND Flash Definitions 171 */ 172 #define CONFIG_NAND_FSL_IFC 173 174 #define CONFIG_SYS_NAND_BASE 0x7e800000 175 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 176 177 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 178 179 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 180 | CSPR_PORT_SIZE_8 \ 181 | CSPR_MSEL_NAND \ 182 | CSPR_V) 183 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 184 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 185 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 186 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 187 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 188 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 189 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 190 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 191 192 #define CONFIG_SYS_NAND_ONFI_DETECTION 193 194 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 195 FTIM0_NAND_TWP(0x18) | \ 196 FTIM0_NAND_TWCHT(0x7) | \ 197 FTIM0_NAND_TWH(0xa)) 198 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 199 FTIM1_NAND_TWBE(0x39) | \ 200 FTIM1_NAND_TRR(0xe) | \ 201 FTIM1_NAND_TRP(0x18)) 202 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 203 FTIM2_NAND_TREH(0xa) | \ 204 FTIM2_NAND_TWHRE(0x1e)) 205 #define CONFIG_SYS_NAND_FTIM3 0x0 206 207 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 208 #define CONFIG_SYS_MAX_NAND_DEVICE 1 209 210 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 211 #endif 212 213 /* 214 * QIXIS Definitions 215 */ 216 #define CONFIG_FSL_QIXIS 217 218 #ifdef CONFIG_FSL_QIXIS 219 #define QIXIS_BASE 0x7fb00000 220 #define QIXIS_BASE_PHYS QIXIS_BASE 221 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 222 #define QIXIS_LBMAP_SWITCH 6 223 #define QIXIS_LBMAP_MASK 0x0f 224 #define QIXIS_LBMAP_SHIFT 0 225 #define QIXIS_LBMAP_DFLTBANK 0x00 226 #define QIXIS_LBMAP_ALTBANK 0x04 227 #define QIXIS_PWR_CTL 0x21 228 #define QIXIS_PWR_CTL_POWEROFF 0x80 229 #define QIXIS_RST_CTL_RESET 0x44 230 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 231 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 232 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 233 #define QIXIS_CTL_SYS 0x5 234 #define QIXIS_CTL_SYS_EVTSW_MASK 0x0c 235 #define QIXIS_CTL_SYS_EVTSW_IRQ 0x04 236 #define QIXIS_RST_FORCE_3 0x45 237 #define QIXIS_RST_FORCE_3_PCIESLOT1 0x80 238 #define QIXIS_PWR_CTL2 0x21 239 #define QIXIS_PWR_CTL2_PCTL 0x2 240 241 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 242 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 243 CSPR_PORT_SIZE_8 | \ 244 CSPR_MSEL_GPCM | \ 245 CSPR_V) 246 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 247 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 248 CSOR_NOR_NOR_MODE_AVD_NOR | \ 249 CSOR_NOR_TRHZ_80) 250 251 /* 252 * QIXIS Timing parameters for IFC GPCM 253 */ 254 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \ 255 FTIM0_GPCM_TEADC(0xe) | \ 256 FTIM0_GPCM_TEAHC(0xe)) 257 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \ 258 FTIM1_GPCM_TRAD(0x1f)) 259 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \ 260 FTIM2_GPCM_TCH(0xe) | \ 261 FTIM2_GPCM_TWP(0xf0)) 262 #define CONFIG_SYS_FPGA_FTIM3 0x0 263 #endif 264 265 #if defined(CONFIG_NAND_BOOT) 266 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 267 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 268 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 269 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 270 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 271 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 272 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 273 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 274 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 275 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 276 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 277 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 278 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 279 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 280 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 281 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 282 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 283 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 284 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 285 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 286 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 287 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 288 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 289 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 290 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 291 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 292 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 293 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 294 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 295 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 296 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 297 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 298 #else 299 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 300 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 301 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 302 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 303 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 304 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 305 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 306 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 307 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 308 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 309 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 310 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 311 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 312 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 313 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 314 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 315 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 316 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 317 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 318 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 319 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 320 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 321 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 322 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 323 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 324 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 325 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 326 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 327 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 328 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 329 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 330 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 331 #endif 332 333 /* 334 * Serial Port 335 */ 336 #ifdef CONFIG_LPUART 337 #define CONFIG_LPUART_32B_REG 338 #else 339 #define CONFIG_SYS_NS16550_SERIAL 340 #ifndef CONFIG_DM_SERIAL 341 #define CONFIG_SYS_NS16550_REG_SIZE 1 342 #endif 343 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 344 #endif 345 346 /* 347 * I2C 348 */ 349 #define CONFIG_SYS_I2C 350 #define CONFIG_SYS_I2C_MXC 351 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 352 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 353 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 354 355 /* 356 * I2C bus multiplexer 357 */ 358 #define I2C_MUX_PCA_ADDR_PRI 0x77 359 #define I2C_MUX_CH_DEFAULT 0x8 360 #define I2C_MUX_CH_CH7301 0xC 361 362 /* 363 * MMC 364 */ 365 #define CONFIG_FSL_ESDHC 366 367 /* SPI */ 368 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 369 /* QSPI */ 370 #define QSPI0_AMBA_BASE 0x40000000 371 #define FSL_QSPI_FLASH_SIZE (1 << 24) 372 #define FSL_QSPI_FLASH_NUM 2 373 374 /* DSPI */ 375 376 /* DM SPI */ 377 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 378 #define CONFIG_DM_SPI_FLASH 379 #define CONFIG_SPI_FLASH_DATAFLASH 380 #endif 381 #endif 382 383 /* 384 * Video 385 */ 386 #ifdef CONFIG_VIDEO_FSL_DCU_FB 387 #define CONFIG_VIDEO_LOGO 388 #define CONFIG_VIDEO_BMP_LOGO 389 390 #define CONFIG_FSL_DIU_CH7301 391 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0 392 #define CONFIG_SYS_I2C_QIXIS_ADDR 0x66 393 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 394 #endif 395 396 /* 397 * eTSEC 398 */ 399 #define CONFIG_TSEC_ENET 400 401 #ifdef CONFIG_TSEC_ENET 402 #define CONFIG_MII 403 #define CONFIG_MII_DEFAULT_TSEC 3 404 #define CONFIG_TSEC1 1 405 #define CONFIG_TSEC1_NAME "eTSEC1" 406 #define CONFIG_TSEC2 1 407 #define CONFIG_TSEC2_NAME "eTSEC2" 408 #define CONFIG_TSEC3 1 409 #define CONFIG_TSEC3_NAME "eTSEC3" 410 411 #define TSEC1_PHY_ADDR 1 412 #define TSEC2_PHY_ADDR 2 413 #define TSEC3_PHY_ADDR 3 414 415 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 416 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 417 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 418 419 #define TSEC1_PHYIDX 0 420 #define TSEC2_PHYIDX 0 421 #define TSEC3_PHYIDX 0 422 423 #define CONFIG_ETHPRIME "eTSEC1" 424 425 #define CONFIG_PHY_REALTEK 426 427 #define CONFIG_HAS_ETH0 428 #define CONFIG_HAS_ETH1 429 #define CONFIG_HAS_ETH2 430 431 #define CONFIG_FSL_SGMII_RISER 1 432 #define SGMII_RISER_PHY_OFFSET 0x1b 433 434 #ifdef CONFIG_FSL_SGMII_RISER 435 #define CONFIG_SYS_TBIPA_VALUE 8 436 #endif 437 438 #endif 439 440 /* PCIe */ 441 #define CONFIG_PCIE1 /* PCIE controller 1 */ 442 #define CONFIG_PCIE2 /* PCIE controller 2 */ 443 444 #ifdef CONFIG_PCI 445 #define CONFIG_PCI_SCAN_SHOW 446 #endif 447 448 #define CONFIG_CMDLINE_TAG 449 450 #define CONFIG_PEN_ADDR_BIG_ENDIAN 451 #define CONFIG_LAYERSCAPE_NS_ACCESS 452 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 453 #define COUNTER_FREQUENCY 12500000 454 455 #define CONFIG_HWCONFIG 456 #define HWCONFIG_BUFFER_SIZE 256 457 458 #define CONFIG_FSL_DEVICE_DISABLE 459 460 461 #define CONFIG_SYS_QE_FW_ADDR 0x60940000 462 463 #ifdef CONFIG_LPUART 464 #define CONFIG_EXTRA_ENV_SETTINGS \ 465 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ 466 "fdt_high=0xffffffff\0" \ 467 "initrd_high=0xffffffff\0" \ 468 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 469 #else 470 #define CONFIG_EXTRA_ENV_SETTINGS \ 471 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 472 "fdt_high=0xffffffff\0" \ 473 "initrd_high=0xffffffff\0" \ 474 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 475 #endif 476 477 /* 478 * Miscellaneous configurable options 479 */ 480 481 #define CONFIG_SYS_MEMTEST_START 0x80000000 482 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 483 484 #define CONFIG_SYS_LOAD_ADDR 0x82000000 485 486 #define CONFIG_LS102XA_STREAM_ID 487 488 #define CONFIG_SYS_INIT_SP_OFFSET \ 489 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 490 #define CONFIG_SYS_INIT_SP_ADDR \ 491 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 492 493 #ifdef CONFIG_SPL_BUILD 494 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 495 #else 496 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 497 #endif 498 499 /* 500 * Environment 501 */ 502 #define CONFIG_ENV_OVERWRITE 503 504 #if defined(CONFIG_SD_BOOT) 505 #define CONFIG_ENV_OFFSET 0x300000 506 #define CONFIG_SYS_MMC_ENV_DEV 0 507 #define CONFIG_ENV_SIZE 0x2000 508 #elif defined(CONFIG_QSPI_BOOT) 509 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 510 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ 511 #define CONFIG_ENV_SECT_SIZE 0x10000 512 #elif defined(CONFIG_NAND_BOOT) 513 #define CONFIG_ENV_SIZE 0x2000 514 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 515 #else 516 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 517 #define CONFIG_ENV_SIZE 0x2000 518 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 519 #endif 520 521 #define CONFIG_MISC_INIT_R 522 523 #include <asm/fsl_secure_boot.h> 524 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 525 526 #endif 527