1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_LS102XA 11 12 #define CONFIG_ARMV7_PSCI_1_0 13 14 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 15 16 #define CONFIG_SYS_FSL_CLK 17 18 #define CONFIG_SKIP_LOWLEVEL_INIT 19 #define CONFIG_BOARD_EARLY_INIT_F 20 21 #define CONFIG_DEEP_SLEEP 22 #if defined(CONFIG_DEEP_SLEEP) 23 #define CONFIG_SILENT_CONSOLE 24 #endif 25 26 /* 27 * Size of malloc() pool 28 */ 29 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 30 31 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 32 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 33 34 /* 35 * Generic Timer Definitions 36 */ 37 #define GENERIC_TIMER_CLK 12500000 38 39 #ifndef __ASSEMBLY__ 40 unsigned long get_board_sys_clk(void); 41 unsigned long get_board_ddr_clk(void); 42 #endif 43 44 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 45 #define CONFIG_SYS_CLK_FREQ 100000000 46 #define CONFIG_DDR_CLK_FREQ 100000000 47 #define CONFIG_QIXIS_I2C_ACCESS 48 #else 49 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 50 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 51 #endif 52 53 #ifdef CONFIG_RAMBOOT_PBL 54 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg 55 #endif 56 57 #ifdef CONFIG_SD_BOOT 58 #ifdef CONFIG_SD_BOOT_QSPI 59 #define CONFIG_SYS_FSL_PBL_RCW \ 60 board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg 61 #else 62 #define CONFIG_SYS_FSL_PBL_RCW \ 63 board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg 64 #endif 65 #define CONFIG_SPL_FRAMEWORK 66 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 67 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 68 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x600 69 70 #define CONFIG_SPL_TEXT_BASE 0x10000000 71 #define CONFIG_SPL_MAX_SIZE 0x1a000 72 #define CONFIG_SPL_STACK 0x1001d000 73 #define CONFIG_SPL_PAD_TO 0x1c000 74 #define CONFIG_SYS_TEXT_BASE 0x82000000 75 76 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 77 CONFIG_SYS_MONITOR_LEN) 78 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 79 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 80 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 81 #define CONFIG_SYS_MONITOR_LEN 0xc0000 82 #endif 83 84 #ifdef CONFIG_QSPI_BOOT 85 #define CONFIG_SYS_TEXT_BASE 0x40010000 86 #endif 87 88 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 89 #define CONFIG_SYS_NO_FLASH 90 #endif 91 92 #ifdef CONFIG_NAND_BOOT 93 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg 94 #define CONFIG_SPL_FRAMEWORK 95 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 96 97 #define CONFIG_SPL_TEXT_BASE 0x10000000 98 #define CONFIG_SPL_MAX_SIZE 0x1a000 99 #define CONFIG_SPL_STACK 0x1001d000 100 #define CONFIG_SPL_PAD_TO 0x1c000 101 #define CONFIG_SYS_TEXT_BASE 0x82000000 102 103 #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10) 104 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 105 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 106 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 107 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 108 109 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 110 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 111 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 112 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 113 #define CONFIG_SYS_MONITOR_LEN 0x80000 114 #endif 115 116 #ifndef CONFIG_SYS_TEXT_BASE 117 #define CONFIG_SYS_TEXT_BASE 0x60100000 118 #endif 119 120 #define CONFIG_NR_DRAM_BANKS 1 121 122 #define CONFIG_DDR_SPD 123 #define SPD_EEPROM_ADDRESS 0x51 124 #define CONFIG_SYS_SPD_BUS_NUM 0 125 126 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 127 #ifndef CONFIG_SYS_FSL_DDR4 128 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ 129 #define CONFIG_SYS_DDR_RAW_TIMING 130 #endif 131 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 132 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 133 134 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 135 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 136 137 #define CONFIG_DDR_ECC 138 #ifdef CONFIG_DDR_ECC 139 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 140 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 141 #endif 142 143 #define CONFIG_SYS_HAS_SERDES 144 145 #define CONFIG_FSL_CAAM /* Enable CAAM */ 146 147 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ 148 !defined(CONFIG_QSPI_BOOT) 149 #define CONFIG_U_QE 150 #endif 151 152 /* 153 * IFC Definitions 154 */ 155 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 156 #define CONFIG_FSL_IFC 157 #define CONFIG_SYS_FLASH_BASE 0x60000000 158 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 159 160 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 161 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 162 CSPR_PORT_SIZE_16 | \ 163 CSPR_MSEL_NOR | \ 164 CSPR_V) 165 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 166 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 167 + 0x8000000) | \ 168 CSPR_PORT_SIZE_16 | \ 169 CSPR_MSEL_NOR | \ 170 CSPR_V) 171 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 172 173 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 174 CSOR_NOR_TRHZ_80) 175 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 176 FTIM0_NOR_TEADC(0x5) | \ 177 FTIM0_NOR_TEAHC(0x5)) 178 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 179 FTIM1_NOR_TRAD_NOR(0x1a) | \ 180 FTIM1_NOR_TSEQRAD_NOR(0x13)) 181 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 182 FTIM2_NOR_TCH(0x4) | \ 183 FTIM2_NOR_TWPH(0xe) | \ 184 FTIM2_NOR_TWP(0x1c)) 185 #define CONFIG_SYS_NOR_FTIM3 0 186 187 #define CONFIG_FLASH_CFI_DRIVER 188 #define CONFIG_SYS_FLASH_CFI 189 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 190 #define CONFIG_SYS_FLASH_QUIET_TEST 191 #define CONFIG_FLASH_SHOW_PROGRESS 45 192 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 193 #define CONFIG_SYS_WRITE_SWAPPED_DATA 194 195 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 196 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 197 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 198 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 199 200 #define CONFIG_SYS_FLASH_EMPTY_INFO 201 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 202 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 203 204 /* 205 * NAND Flash Definitions 206 */ 207 #define CONFIG_NAND_FSL_IFC 208 209 #define CONFIG_SYS_NAND_BASE 0x7e800000 210 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 211 212 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 213 214 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 215 | CSPR_PORT_SIZE_8 \ 216 | CSPR_MSEL_NAND \ 217 | CSPR_V) 218 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 219 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 220 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 221 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 222 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 223 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 224 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 225 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 226 227 #define CONFIG_SYS_NAND_ONFI_DETECTION 228 229 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 230 FTIM0_NAND_TWP(0x18) | \ 231 FTIM0_NAND_TWCHT(0x7) | \ 232 FTIM0_NAND_TWH(0xa)) 233 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 234 FTIM1_NAND_TWBE(0x39) | \ 235 FTIM1_NAND_TRR(0xe) | \ 236 FTIM1_NAND_TRP(0x18)) 237 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 238 FTIM2_NAND_TREH(0xa) | \ 239 FTIM2_NAND_TWHRE(0x1e)) 240 #define CONFIG_SYS_NAND_FTIM3 0x0 241 242 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 243 #define CONFIG_SYS_MAX_NAND_DEVICE 1 244 #define CONFIG_CMD_NAND 245 246 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 247 #endif 248 249 /* 250 * QIXIS Definitions 251 */ 252 #define CONFIG_FSL_QIXIS 253 254 #ifdef CONFIG_FSL_QIXIS 255 #define QIXIS_BASE 0x7fb00000 256 #define QIXIS_BASE_PHYS QIXIS_BASE 257 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 258 #define QIXIS_LBMAP_SWITCH 6 259 #define QIXIS_LBMAP_MASK 0x0f 260 #define QIXIS_LBMAP_SHIFT 0 261 #define QIXIS_LBMAP_DFLTBANK 0x00 262 #define QIXIS_LBMAP_ALTBANK 0x04 263 #define QIXIS_PWR_CTL 0x21 264 #define QIXIS_PWR_CTL_POWEROFF 0x80 265 #define QIXIS_RST_CTL_RESET 0x44 266 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 267 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 268 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 269 #define QIXIS_CTL_SYS 0x5 270 #define QIXIS_CTL_SYS_EVTSW_MASK 0x0c 271 #define QIXIS_CTL_SYS_EVTSW_IRQ 0x04 272 #define QIXIS_RST_FORCE_3 0x45 273 #define QIXIS_RST_FORCE_3_PCIESLOT1 0x80 274 #define QIXIS_PWR_CTL2 0x21 275 #define QIXIS_PWR_CTL2_PCTL 0x2 276 277 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 278 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 279 CSPR_PORT_SIZE_8 | \ 280 CSPR_MSEL_GPCM | \ 281 CSPR_V) 282 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 283 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 284 CSOR_NOR_NOR_MODE_AVD_NOR | \ 285 CSOR_NOR_TRHZ_80) 286 287 /* 288 * QIXIS Timing parameters for IFC GPCM 289 */ 290 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \ 291 FTIM0_GPCM_TEADC(0xe) | \ 292 FTIM0_GPCM_TEAHC(0xe)) 293 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \ 294 FTIM1_GPCM_TRAD(0x1f)) 295 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \ 296 FTIM2_GPCM_TCH(0xe) | \ 297 FTIM2_GPCM_TWP(0xf0)) 298 #define CONFIG_SYS_FPGA_FTIM3 0x0 299 #endif 300 301 #if defined(CONFIG_NAND_BOOT) 302 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 303 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 304 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 305 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 306 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 307 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 308 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 309 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 310 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 311 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 312 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 313 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 314 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 315 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 316 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 317 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 318 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 319 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 320 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 321 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 322 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 323 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 324 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 325 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 326 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 327 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 328 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 329 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 330 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 331 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 332 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 333 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 334 #else 335 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 336 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 337 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 338 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 339 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 340 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 341 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 342 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 343 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 344 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 345 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 346 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 347 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 348 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 349 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 350 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 351 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 352 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 353 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 354 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 355 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 356 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 357 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 358 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 359 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 360 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 361 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 362 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 363 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 364 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 365 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 366 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 367 #endif 368 369 /* 370 * Serial Port 371 */ 372 #ifdef CONFIG_LPUART 373 #define CONFIG_LPUART_32B_REG 374 #else 375 #define CONFIG_CONS_INDEX 1 376 #define CONFIG_SYS_NS16550_SERIAL 377 #ifndef CONFIG_DM_SERIAL 378 #define CONFIG_SYS_NS16550_REG_SIZE 1 379 #endif 380 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 381 #endif 382 383 #define CONFIG_BAUDRATE 115200 384 385 /* 386 * I2C 387 */ 388 #define CONFIG_SYS_I2C 389 #define CONFIG_SYS_I2C_MXC 390 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 391 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 392 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 393 394 /* 395 * I2C bus multiplexer 396 */ 397 #define I2C_MUX_PCA_ADDR_PRI 0x77 398 #define I2C_MUX_CH_DEFAULT 0x8 399 #define I2C_MUX_CH_CH7301 0xC 400 401 /* 402 * MMC 403 */ 404 #define CONFIG_MMC 405 #define CONFIG_FSL_ESDHC 406 #define CONFIG_GENERIC_MMC 407 408 #define CONFIG_DOS_PARTITION 409 410 /* SPI */ 411 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 412 /* QSPI */ 413 #define QSPI0_AMBA_BASE 0x40000000 414 #define FSL_QSPI_FLASH_SIZE (1 << 24) 415 #define FSL_QSPI_FLASH_NUM 2 416 417 /* DSPI */ 418 419 /* DM SPI */ 420 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 421 #define CONFIG_DM_SPI_FLASH 422 #define CONFIG_SPI_FLASH_DATAFLASH 423 #endif 424 #endif 425 426 /* 427 * USB 428 */ 429 /* EHCI Support - disbaled by default */ 430 /*#define CONFIG_HAS_FSL_DR_USB*/ 431 432 #ifdef CONFIG_HAS_FSL_DR_USB 433 #define CONFIG_USB_EHCI 434 #define CONFIG_USB_EHCI_FSL 435 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 436 #endif 437 438 /*XHCI Support - enabled by default*/ 439 #define CONFIG_HAS_FSL_XHCI_USB 440 441 #ifdef CONFIG_HAS_FSL_XHCI_USB 442 #define CONFIG_USB_XHCI_FSL 443 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 444 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 445 #endif 446 447 /* 448 * Video 449 */ 450 #define CONFIG_FSL_DCU_FB 451 452 #ifdef CONFIG_FSL_DCU_FB 453 #define CONFIG_VIDEO 454 #define CONFIG_CMD_BMP 455 #define CONFIG_CFB_CONSOLE 456 #define CONFIG_VGA_AS_SINGLE_DEVICE 457 #define CONFIG_VIDEO_LOGO 458 #define CONFIG_VIDEO_BMP_LOGO 459 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 460 461 #define CONFIG_FSL_DIU_CH7301 462 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0 463 #define CONFIG_SYS_I2C_QIXIS_ADDR 0x66 464 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 465 #endif 466 467 /* 468 * eTSEC 469 */ 470 #define CONFIG_TSEC_ENET 471 472 #ifdef CONFIG_TSEC_ENET 473 #define CONFIG_MII 474 #define CONFIG_MII_DEFAULT_TSEC 3 475 #define CONFIG_TSEC1 1 476 #define CONFIG_TSEC1_NAME "eTSEC1" 477 #define CONFIG_TSEC2 1 478 #define CONFIG_TSEC2_NAME "eTSEC2" 479 #define CONFIG_TSEC3 1 480 #define CONFIG_TSEC3_NAME "eTSEC3" 481 482 #define TSEC1_PHY_ADDR 1 483 #define TSEC2_PHY_ADDR 2 484 #define TSEC3_PHY_ADDR 3 485 486 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 487 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 488 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 489 490 #define TSEC1_PHYIDX 0 491 #define TSEC2_PHYIDX 0 492 #define TSEC3_PHYIDX 0 493 494 #define CONFIG_ETHPRIME "eTSEC1" 495 496 #define CONFIG_PHY_GIGE 497 #define CONFIG_PHYLIB 498 #define CONFIG_PHY_REALTEK 499 500 #define CONFIG_HAS_ETH0 501 #define CONFIG_HAS_ETH1 502 #define CONFIG_HAS_ETH2 503 504 #define CONFIG_FSL_SGMII_RISER 1 505 #define SGMII_RISER_PHY_OFFSET 0x1b 506 507 #ifdef CONFIG_FSL_SGMII_RISER 508 #define CONFIG_SYS_TBIPA_VALUE 8 509 #endif 510 511 #endif 512 513 /* PCIe */ 514 #define CONFIG_PCI /* Enable PCI/PCIE */ 515 #define CONFIG_PCIE1 /* PCIE controller 1 */ 516 #define CONFIG_PCIE2 /* PCIE controller 2 */ 517 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 518 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" 519 520 #define CONFIG_SYS_PCI_64BIT 521 522 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 523 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ 524 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 525 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ 526 527 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 528 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 529 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ 530 531 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 532 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 533 #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ 534 535 #ifdef CONFIG_PCI 536 #define CONFIG_PCI_PNP 537 #define CONFIG_PCI_SCAN_SHOW 538 #define CONFIG_CMD_PCI 539 #endif 540 541 #define CONFIG_CMDLINE_TAG 542 #define CONFIG_CMDLINE_EDITING 543 544 #define CONFIG_ARMV7_NONSEC 545 #define CONFIG_ARMV7_VIRT 546 #define CONFIG_PEN_ADDR_BIG_ENDIAN 547 #define CONFIG_LAYERSCAPE_NS_ACCESS 548 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 549 #define CONFIG_TIMER_CLK_FREQ 12500000 550 551 #define CONFIG_HWCONFIG 552 #define HWCONFIG_BUFFER_SIZE 256 553 554 #define CONFIG_FSL_DEVICE_DISABLE 555 556 557 #define CONFIG_SYS_QE_FW_ADDR 0x600c0000 558 559 #ifdef CONFIG_LPUART 560 #define CONFIG_EXTRA_ENV_SETTINGS \ 561 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ 562 "fdt_high=0xffffffff\0" \ 563 "initrd_high=0xffffffff\0" \ 564 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 565 #else 566 #define CONFIG_EXTRA_ENV_SETTINGS \ 567 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 568 "fdt_high=0xffffffff\0" \ 569 "initrd_high=0xffffffff\0" \ 570 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 571 #endif 572 573 /* 574 * Miscellaneous configurable options 575 */ 576 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 577 #define CONFIG_AUTO_COMPLETE 578 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 579 #define CONFIG_SYS_PBSIZE \ 580 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 581 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 582 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 583 584 #define CONFIG_SYS_MEMTEST_START 0x80000000 585 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 586 587 #define CONFIG_SYS_LOAD_ADDR 0x82000000 588 589 #define CONFIG_LS102XA_STREAM_ID 590 591 /* 592 * Stack sizes 593 * The stack sizes are set up in start.S using the settings below 594 */ 595 #define CONFIG_STACKSIZE (30 * 1024) 596 597 #define CONFIG_SYS_INIT_SP_OFFSET \ 598 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 599 #define CONFIG_SYS_INIT_SP_ADDR \ 600 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 601 602 #ifdef CONFIG_SPL_BUILD 603 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 604 #else 605 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 606 #endif 607 608 /* 609 * Environment 610 */ 611 #define CONFIG_ENV_OVERWRITE 612 613 #if defined(CONFIG_SD_BOOT) 614 #define CONFIG_ENV_OFFSET 0x100000 615 #define CONFIG_ENV_IS_IN_MMC 616 #define CONFIG_SYS_MMC_ENV_DEV 0 617 #define CONFIG_ENV_SIZE 0x2000 618 #elif defined(CONFIG_QSPI_BOOT) 619 #define CONFIG_ENV_IS_IN_SPI_FLASH 620 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 621 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 622 #define CONFIG_ENV_SECT_SIZE 0x10000 623 #elif defined(CONFIG_NAND_BOOT) 624 #define CONFIG_ENV_IS_IN_NAND 625 #define CONFIG_ENV_SIZE 0x2000 626 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 627 #else 628 #define CONFIG_ENV_IS_IN_FLASH 629 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 630 #define CONFIG_ENV_SIZE 0x2000 631 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 632 #endif 633 634 #define CONFIG_MISC_INIT_R 635 636 /* Hash command with SHA acceleration supported in hardware */ 637 #ifdef CONFIG_FSL_CAAM 638 #define CONFIG_CMD_HASH 639 #define CONFIG_SHA_HW_ACCEL 640 #endif 641 642 #include <asm/fsl_secure_boot.h> 643 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 644 645 #endif 646