1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_LS102XA 11 12 #define CONFIG_ARMV7_PSCI 13 #define CONFIG_ARMV7_PSCI_1_0 14 #define CONFIG_ARMV7_PSCI_NR_CPUS CONFIG_MAX_CPUS 15 16 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 17 18 #define CONFIG_SYS_FSL_CLK 19 20 #define CONFIG_DISPLAY_CPUINFO 21 #define CONFIG_DISPLAY_BOARDINFO 22 23 #define CONFIG_SKIP_LOWLEVEL_INIT 24 #define CONFIG_BOARD_EARLY_INIT_F 25 26 #define CONFIG_DEEP_SLEEP 27 #if defined(CONFIG_DEEP_SLEEP) 28 #define CONFIG_SILENT_CONSOLE 29 #endif 30 31 /* 32 * Size of malloc() pool 33 */ 34 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 35 36 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 37 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 38 39 /* 40 * Generic Timer Definitions 41 */ 42 #define GENERIC_TIMER_CLK 12500000 43 44 #ifndef __ASSEMBLY__ 45 unsigned long get_board_sys_clk(void); 46 unsigned long get_board_ddr_clk(void); 47 #endif 48 49 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 50 #define CONFIG_SYS_CLK_FREQ 100000000 51 #define CONFIG_DDR_CLK_FREQ 100000000 52 #define CONFIG_QIXIS_I2C_ACCESS 53 #else 54 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 55 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 56 #endif 57 58 #ifdef CONFIG_RAMBOOT_PBL 59 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg 60 #endif 61 62 #ifdef CONFIG_SD_BOOT 63 #ifdef CONFIG_SD_BOOT_QSPI 64 #define CONFIG_SYS_FSL_PBL_RCW \ 65 board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg 66 #else 67 #define CONFIG_SYS_FSL_PBL_RCW \ 68 board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg 69 #endif 70 #define CONFIG_SPL_FRAMEWORK 71 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 72 #define CONFIG_SPL_LIBCOMMON_SUPPORT 73 #define CONFIG_SPL_LIBGENERIC_SUPPORT 74 #define CONFIG_SPL_ENV_SUPPORT 75 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 76 #define CONFIG_SPL_I2C_SUPPORT 77 #define CONFIG_SPL_WATCHDOG_SUPPORT 78 #define CONFIG_SPL_SERIAL_SUPPORT 79 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 80 #define CONFIG_SPL_MMC_SUPPORT 81 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 82 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x600 83 84 #define CONFIG_SPL_TEXT_BASE 0x10000000 85 #define CONFIG_SPL_MAX_SIZE 0x1a000 86 #define CONFIG_SPL_STACK 0x1001d000 87 #define CONFIG_SPL_PAD_TO 0x1c000 88 #define CONFIG_SYS_TEXT_BASE 0x82000000 89 90 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 91 CONFIG_SYS_MONITOR_LEN) 92 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 93 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 94 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 95 #define CONFIG_SYS_MONITOR_LEN 0xc0000 96 #endif 97 98 #ifdef CONFIG_QSPI_BOOT 99 #define CONFIG_SYS_TEXT_BASE 0x40010000 100 #endif 101 102 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 103 #define CONFIG_SYS_NO_FLASH 104 #endif 105 106 #ifdef CONFIG_NAND_BOOT 107 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg 108 #define CONFIG_SPL_FRAMEWORK 109 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 110 #define CONFIG_SPL_LIBCOMMON_SUPPORT 111 #define CONFIG_SPL_LIBGENERIC_SUPPORT 112 #define CONFIG_SPL_ENV_SUPPORT 113 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 114 #define CONFIG_SPL_I2C_SUPPORT 115 #define CONFIG_SPL_WATCHDOG_SUPPORT 116 #define CONFIG_SPL_SERIAL_SUPPORT 117 #define CONFIG_SPL_NAND_SUPPORT 118 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 119 120 #define CONFIG_SPL_TEXT_BASE 0x10000000 121 #define CONFIG_SPL_MAX_SIZE 0x1a000 122 #define CONFIG_SPL_STACK 0x1001d000 123 #define CONFIG_SPL_PAD_TO 0x1c000 124 #define CONFIG_SYS_TEXT_BASE 0x82000000 125 126 #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10) 127 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 128 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 129 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 130 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 131 132 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 133 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 134 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 135 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 136 #define CONFIG_SYS_MONITOR_LEN 0x80000 137 #endif 138 139 #ifndef CONFIG_SYS_TEXT_BASE 140 #define CONFIG_SYS_TEXT_BASE 0x60100000 141 #endif 142 143 #define CONFIG_NR_DRAM_BANKS 1 144 145 #define CONFIG_DDR_SPD 146 #define SPD_EEPROM_ADDRESS 0x51 147 #define CONFIG_SYS_SPD_BUS_NUM 0 148 149 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 150 #ifndef CONFIG_SYS_FSL_DDR4 151 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ 152 #define CONFIG_SYS_DDR_RAW_TIMING 153 #endif 154 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 155 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 156 157 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 158 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 159 160 #define CONFIG_DDR_ECC 161 #ifdef CONFIG_DDR_ECC 162 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 163 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 164 #endif 165 166 #define CONFIG_SYS_HAS_SERDES 167 168 #define CONFIG_FSL_CAAM /* Enable CAAM */ 169 170 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ 171 !defined(CONFIG_QSPI_BOOT) 172 #define CONFIG_U_QE 173 #endif 174 175 /* 176 * IFC Definitions 177 */ 178 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 179 #define CONFIG_FSL_IFC 180 #define CONFIG_SYS_FLASH_BASE 0x60000000 181 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 182 183 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 184 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 185 CSPR_PORT_SIZE_16 | \ 186 CSPR_MSEL_NOR | \ 187 CSPR_V) 188 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 189 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 190 + 0x8000000) | \ 191 CSPR_PORT_SIZE_16 | \ 192 CSPR_MSEL_NOR | \ 193 CSPR_V) 194 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 195 196 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 197 CSOR_NOR_TRHZ_80) 198 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 199 FTIM0_NOR_TEADC(0x5) | \ 200 FTIM0_NOR_TEAHC(0x5)) 201 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 202 FTIM1_NOR_TRAD_NOR(0x1a) | \ 203 FTIM1_NOR_TSEQRAD_NOR(0x13)) 204 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 205 FTIM2_NOR_TCH(0x4) | \ 206 FTIM2_NOR_TWPH(0xe) | \ 207 FTIM2_NOR_TWP(0x1c)) 208 #define CONFIG_SYS_NOR_FTIM3 0 209 210 #define CONFIG_FLASH_CFI_DRIVER 211 #define CONFIG_SYS_FLASH_CFI 212 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 213 #define CONFIG_SYS_FLASH_QUIET_TEST 214 #define CONFIG_FLASH_SHOW_PROGRESS 45 215 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 216 #define CONFIG_SYS_WRITE_SWAPPED_DATA 217 218 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 219 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 220 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 221 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 222 223 #define CONFIG_SYS_FLASH_EMPTY_INFO 224 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 225 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 226 227 /* 228 * NAND Flash Definitions 229 */ 230 #define CONFIG_NAND_FSL_IFC 231 232 #define CONFIG_SYS_NAND_BASE 0x7e800000 233 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 234 235 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 236 237 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 238 | CSPR_PORT_SIZE_8 \ 239 | CSPR_MSEL_NAND \ 240 | CSPR_V) 241 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 242 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 243 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 244 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 245 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 246 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 247 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 248 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 249 250 #define CONFIG_SYS_NAND_ONFI_DETECTION 251 252 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 253 FTIM0_NAND_TWP(0x18) | \ 254 FTIM0_NAND_TWCHT(0x7) | \ 255 FTIM0_NAND_TWH(0xa)) 256 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 257 FTIM1_NAND_TWBE(0x39) | \ 258 FTIM1_NAND_TRR(0xe) | \ 259 FTIM1_NAND_TRP(0x18)) 260 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 261 FTIM2_NAND_TREH(0xa) | \ 262 FTIM2_NAND_TWHRE(0x1e)) 263 #define CONFIG_SYS_NAND_FTIM3 0x0 264 265 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 266 #define CONFIG_SYS_MAX_NAND_DEVICE 1 267 #define CONFIG_CMD_NAND 268 269 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 270 #endif 271 272 /* 273 * QIXIS Definitions 274 */ 275 #define CONFIG_FSL_QIXIS 276 277 #ifdef CONFIG_FSL_QIXIS 278 #define QIXIS_BASE 0x7fb00000 279 #define QIXIS_BASE_PHYS QIXIS_BASE 280 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 281 #define QIXIS_LBMAP_SWITCH 6 282 #define QIXIS_LBMAP_MASK 0x0f 283 #define QIXIS_LBMAP_SHIFT 0 284 #define QIXIS_LBMAP_DFLTBANK 0x00 285 #define QIXIS_LBMAP_ALTBANK 0x04 286 #define QIXIS_PWR_CTL 0x21 287 #define QIXIS_PWR_CTL_POWEROFF 0x80 288 #define QIXIS_RST_CTL_RESET 0x44 289 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 290 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 291 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 292 293 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 294 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 295 CSPR_PORT_SIZE_8 | \ 296 CSPR_MSEL_GPCM | \ 297 CSPR_V) 298 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 299 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 300 CSOR_NOR_NOR_MODE_AVD_NOR | \ 301 CSOR_NOR_TRHZ_80) 302 303 /* 304 * QIXIS Timing parameters for IFC GPCM 305 */ 306 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \ 307 FTIM0_GPCM_TEADC(0xe) | \ 308 FTIM0_GPCM_TEAHC(0xe)) 309 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \ 310 FTIM1_GPCM_TRAD(0x1f)) 311 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \ 312 FTIM2_GPCM_TCH(0xe) | \ 313 FTIM2_GPCM_TWP(0xf0)) 314 #define CONFIG_SYS_FPGA_FTIM3 0x0 315 #endif 316 317 #if defined(CONFIG_NAND_BOOT) 318 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 319 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 320 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 321 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 322 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 323 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 324 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 325 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 326 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 327 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 328 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 329 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 330 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 331 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 332 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 333 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 334 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 335 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 336 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 337 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 338 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 339 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 340 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 341 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 342 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 343 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 344 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 345 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 346 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 347 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 348 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 349 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 350 #else 351 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 352 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 353 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 354 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 355 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 356 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 357 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 358 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 359 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 360 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 361 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 362 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 363 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 364 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 365 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 366 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 367 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 368 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 369 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 370 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 371 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 372 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 373 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 374 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 375 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 376 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 377 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 378 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 379 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 380 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 381 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 382 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 383 #endif 384 385 /* 386 * Serial Port 387 */ 388 #ifdef CONFIG_LPUART 389 #define CONFIG_LPUART_32B_REG 390 #else 391 #define CONFIG_CONS_INDEX 1 392 #define CONFIG_SYS_NS16550_SERIAL 393 #ifndef CONFIG_DM_SERIAL 394 #define CONFIG_SYS_NS16550_REG_SIZE 1 395 #endif 396 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 397 #endif 398 399 #define CONFIG_BAUDRATE 115200 400 401 /* 402 * I2C 403 */ 404 #define CONFIG_SYS_I2C 405 #define CONFIG_SYS_I2C_MXC 406 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 407 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 408 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 409 410 /* 411 * I2C bus multiplexer 412 */ 413 #define I2C_MUX_PCA_ADDR_PRI 0x77 414 #define I2C_MUX_CH_DEFAULT 0x8 415 #define I2C_MUX_CH_CH7301 0xC 416 417 /* 418 * MMC 419 */ 420 #define CONFIG_MMC 421 #define CONFIG_FSL_ESDHC 422 #define CONFIG_GENERIC_MMC 423 424 #define CONFIG_DOS_PARTITION 425 426 /* SPI */ 427 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 428 /* QSPI */ 429 #define QSPI0_AMBA_BASE 0x40000000 430 #define FSL_QSPI_FLASH_SIZE (1 << 24) 431 #define FSL_QSPI_FLASH_NUM 2 432 433 /* DSPI */ 434 435 /* DM SPI */ 436 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 437 #define CONFIG_DM_SPI_FLASH 438 #define CONFIG_SPI_FLASH_DATAFLASH 439 #endif 440 #endif 441 442 /* 443 * USB 444 */ 445 /* EHCI Support - disbaled by default */ 446 /*#define CONFIG_HAS_FSL_DR_USB*/ 447 448 #ifdef CONFIG_HAS_FSL_DR_USB 449 #define CONFIG_USB_EHCI 450 #define CONFIG_USB_EHCI_FSL 451 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 452 #endif 453 454 /*XHCI Support - enabled by default*/ 455 #define CONFIG_HAS_FSL_XHCI_USB 456 457 #ifdef CONFIG_HAS_FSL_XHCI_USB 458 #define CONFIG_USB_XHCI_FSL 459 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 460 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 461 #endif 462 463 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB) 464 #define CONFIG_USB_STORAGE 465 #endif 466 467 /* 468 * Video 469 */ 470 #define CONFIG_FSL_DCU_FB 471 472 #ifdef CONFIG_FSL_DCU_FB 473 #define CONFIG_VIDEO 474 #define CONFIG_CMD_BMP 475 #define CONFIG_CFB_CONSOLE 476 #define CONFIG_VGA_AS_SINGLE_DEVICE 477 #define CONFIG_VIDEO_LOGO 478 #define CONFIG_VIDEO_BMP_LOGO 479 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 480 481 #define CONFIG_FSL_DIU_CH7301 482 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0 483 #define CONFIG_SYS_I2C_QIXIS_ADDR 0x66 484 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 485 #endif 486 487 /* 488 * eTSEC 489 */ 490 #define CONFIG_TSEC_ENET 491 492 #ifdef CONFIG_TSEC_ENET 493 #define CONFIG_MII 494 #define CONFIG_MII_DEFAULT_TSEC 3 495 #define CONFIG_TSEC1 1 496 #define CONFIG_TSEC1_NAME "eTSEC1" 497 #define CONFIG_TSEC2 1 498 #define CONFIG_TSEC2_NAME "eTSEC2" 499 #define CONFIG_TSEC3 1 500 #define CONFIG_TSEC3_NAME "eTSEC3" 501 502 #define TSEC1_PHY_ADDR 1 503 #define TSEC2_PHY_ADDR 2 504 #define TSEC3_PHY_ADDR 3 505 506 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 507 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 508 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 509 510 #define TSEC1_PHYIDX 0 511 #define TSEC2_PHYIDX 0 512 #define TSEC3_PHYIDX 0 513 514 #define CONFIG_ETHPRIME "eTSEC1" 515 516 #define CONFIG_PHY_GIGE 517 #define CONFIG_PHYLIB 518 #define CONFIG_PHY_REALTEK 519 520 #define CONFIG_HAS_ETH0 521 #define CONFIG_HAS_ETH1 522 #define CONFIG_HAS_ETH2 523 524 #define CONFIG_FSL_SGMII_RISER 1 525 #define SGMII_RISER_PHY_OFFSET 0x1b 526 527 #ifdef CONFIG_FSL_SGMII_RISER 528 #define CONFIG_SYS_TBIPA_VALUE 8 529 #endif 530 531 #endif 532 533 /* PCIe */ 534 #define CONFIG_PCI /* Enable PCI/PCIE */ 535 #define CONFIG_PCIE1 /* PCIE controller 1 */ 536 #define CONFIG_PCIE2 /* PCIE controller 2 */ 537 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 538 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" 539 540 #define CONFIG_SYS_PCI_64BIT 541 542 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 543 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ 544 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 545 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ 546 547 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 548 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 549 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ 550 551 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 552 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 553 #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ 554 555 #ifdef CONFIG_PCI 556 #define CONFIG_PCI_PNP 557 #define CONFIG_PCI_SCAN_SHOW 558 #define CONFIG_CMD_PCI 559 #endif 560 561 #define CONFIG_CMDLINE_TAG 562 #define CONFIG_CMDLINE_EDITING 563 564 #define CONFIG_ARMV7_NONSEC 565 #define CONFIG_ARMV7_VIRT 566 #define CONFIG_PEN_ADDR_BIG_ENDIAN 567 #define CONFIG_LAYERSCAPE_NS_ACCESS 568 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 569 #define CONFIG_TIMER_CLK_FREQ 12500000 570 571 #define CONFIG_HWCONFIG 572 #define HWCONFIG_BUFFER_SIZE 256 573 574 #define CONFIG_FSL_DEVICE_DISABLE 575 576 577 #define CONFIG_SYS_QE_FW_ADDR 0x600c0000 578 579 #ifdef CONFIG_LPUART 580 #define CONFIG_EXTRA_ENV_SETTINGS \ 581 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ 582 "fdt_high=0xffffffff\0" \ 583 "initrd_high=0xffffffff\0" \ 584 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 585 #else 586 #define CONFIG_EXTRA_ENV_SETTINGS \ 587 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 588 "fdt_high=0xffffffff\0" \ 589 "initrd_high=0xffffffff\0" \ 590 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 591 #endif 592 593 /* 594 * Miscellaneous configurable options 595 */ 596 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 597 #define CONFIG_AUTO_COMPLETE 598 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 599 #define CONFIG_SYS_PBSIZE \ 600 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 601 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 602 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 603 604 #define CONFIG_SYS_MEMTEST_START 0x80000000 605 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 606 607 #define CONFIG_SYS_LOAD_ADDR 0x82000000 608 609 #define CONFIG_LS102XA_STREAM_ID 610 611 /* 612 * Stack sizes 613 * The stack sizes are set up in start.S using the settings below 614 */ 615 #define CONFIG_STACKSIZE (30 * 1024) 616 617 #define CONFIG_SYS_INIT_SP_OFFSET \ 618 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 619 #define CONFIG_SYS_INIT_SP_ADDR \ 620 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 621 622 #ifdef CONFIG_SPL_BUILD 623 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 624 #else 625 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 626 #endif 627 628 /* 629 * Environment 630 */ 631 #define CONFIG_ENV_OVERWRITE 632 633 #if defined(CONFIG_SD_BOOT) 634 #define CONFIG_ENV_OFFSET 0x100000 635 #define CONFIG_ENV_IS_IN_MMC 636 #define CONFIG_SYS_MMC_ENV_DEV 0 637 #define CONFIG_ENV_SIZE 0x2000 638 #elif defined(CONFIG_QSPI_BOOT) 639 #define CONFIG_ENV_IS_IN_SPI_FLASH 640 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 641 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 642 #define CONFIG_ENV_SECT_SIZE 0x10000 643 #elif defined(CONFIG_NAND_BOOT) 644 #define CONFIG_ENV_IS_IN_NAND 645 #define CONFIG_ENV_SIZE 0x2000 646 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 647 #else 648 #define CONFIG_ENV_IS_IN_FLASH 649 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 650 #define CONFIG_ENV_SIZE 0x2000 651 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 652 #endif 653 654 #define CONFIG_MISC_INIT_R 655 656 /* Hash command with SHA acceleration supported in hardware */ 657 #ifdef CONFIG_FSL_CAAM 658 #define CONFIG_CMD_HASH 659 #define CONFIG_SHA_HW_ACCEL 660 #endif 661 662 #include <asm/fsl_secure_boot.h> 663 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 664 665 #endif 666