1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_LS102XA 11 12 #define CONFIG_ARMV7_PSCI_1_0 13 14 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 15 16 #define CONFIG_SYS_FSL_CLK 17 18 #define CONFIG_SKIP_LOWLEVEL_INIT 19 #define CONFIG_BOARD_EARLY_INIT_F 20 21 #define CONFIG_DEEP_SLEEP 22 23 /* 24 * Size of malloc() pool 25 */ 26 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 27 28 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 29 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 30 31 /* 32 * Generic Timer Definitions 33 */ 34 #define GENERIC_TIMER_CLK 12500000 35 36 #ifndef __ASSEMBLY__ 37 unsigned long get_board_sys_clk(void); 38 unsigned long get_board_ddr_clk(void); 39 #endif 40 41 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 42 #define CONFIG_SYS_CLK_FREQ 100000000 43 #define CONFIG_DDR_CLK_FREQ 100000000 44 #define CONFIG_QIXIS_I2C_ACCESS 45 #else 46 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 47 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 48 #endif 49 50 #ifdef CONFIG_RAMBOOT_PBL 51 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg 52 #endif 53 54 #ifdef CONFIG_SD_BOOT 55 #ifdef CONFIG_SD_BOOT_QSPI 56 #define CONFIG_SYS_FSL_PBL_RCW \ 57 board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg 58 #else 59 #define CONFIG_SYS_FSL_PBL_RCW \ 60 board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg 61 #endif 62 #define CONFIG_SPL_FRAMEWORK 63 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 64 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 65 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x600 66 67 #define CONFIG_SPL_TEXT_BASE 0x10000000 68 #define CONFIG_SPL_MAX_SIZE 0x1a000 69 #define CONFIG_SPL_STACK 0x1001d000 70 #define CONFIG_SPL_PAD_TO 0x1c000 71 #define CONFIG_SYS_TEXT_BASE 0x82000000 72 73 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 74 CONFIG_SYS_MONITOR_LEN) 75 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 76 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 77 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 78 #define CONFIG_SYS_MONITOR_LEN 0xc0000 79 #endif 80 81 #ifdef CONFIG_QSPI_BOOT 82 #define CONFIG_SYS_TEXT_BASE 0x40010000 83 #endif 84 85 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 86 #define CONFIG_SYS_NO_FLASH 87 #endif 88 89 #ifdef CONFIG_NAND_BOOT 90 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg 91 #define CONFIG_SPL_FRAMEWORK 92 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 93 94 #define CONFIG_SPL_TEXT_BASE 0x10000000 95 #define CONFIG_SPL_MAX_SIZE 0x1a000 96 #define CONFIG_SPL_STACK 0x1001d000 97 #define CONFIG_SPL_PAD_TO 0x1c000 98 #define CONFIG_SYS_TEXT_BASE 0x82000000 99 100 #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10) 101 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 102 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 103 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 104 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 105 106 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 107 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 108 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 109 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 110 #define CONFIG_SYS_MONITOR_LEN 0x80000 111 #endif 112 113 #ifndef CONFIG_SYS_TEXT_BASE 114 #define CONFIG_SYS_TEXT_BASE 0x60100000 115 #endif 116 117 #define CONFIG_NR_DRAM_BANKS 1 118 119 #define CONFIG_DDR_SPD 120 #define SPD_EEPROM_ADDRESS 0x51 121 #define CONFIG_SYS_SPD_BUS_NUM 0 122 123 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 124 #ifndef CONFIG_SYS_FSL_DDR4 125 #define CONFIG_SYS_DDR_RAW_TIMING 126 #endif 127 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 128 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 129 130 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 131 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 132 133 #define CONFIG_DDR_ECC 134 #ifdef CONFIG_DDR_ECC 135 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 136 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 137 #endif 138 139 #define CONFIG_FSL_CAAM /* Enable CAAM */ 140 141 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ 142 !defined(CONFIG_QSPI_BOOT) 143 #define CONFIG_U_QE 144 #endif 145 146 /* 147 * IFC Definitions 148 */ 149 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 150 #define CONFIG_FSL_IFC 151 #define CONFIG_SYS_FLASH_BASE 0x60000000 152 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 153 154 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 155 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 156 CSPR_PORT_SIZE_16 | \ 157 CSPR_MSEL_NOR | \ 158 CSPR_V) 159 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 160 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 161 + 0x8000000) | \ 162 CSPR_PORT_SIZE_16 | \ 163 CSPR_MSEL_NOR | \ 164 CSPR_V) 165 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 166 167 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 168 CSOR_NOR_TRHZ_80) 169 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 170 FTIM0_NOR_TEADC(0x5) | \ 171 FTIM0_NOR_TEAHC(0x5)) 172 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 173 FTIM1_NOR_TRAD_NOR(0x1a) | \ 174 FTIM1_NOR_TSEQRAD_NOR(0x13)) 175 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 176 FTIM2_NOR_TCH(0x4) | \ 177 FTIM2_NOR_TWPH(0xe) | \ 178 FTIM2_NOR_TWP(0x1c)) 179 #define CONFIG_SYS_NOR_FTIM3 0 180 181 #define CONFIG_FLASH_CFI_DRIVER 182 #define CONFIG_SYS_FLASH_CFI 183 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 184 #define CONFIG_SYS_FLASH_QUIET_TEST 185 #define CONFIG_FLASH_SHOW_PROGRESS 45 186 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 187 #define CONFIG_SYS_WRITE_SWAPPED_DATA 188 189 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 190 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 191 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 192 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 193 194 #define CONFIG_SYS_FLASH_EMPTY_INFO 195 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 196 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 197 198 /* 199 * NAND Flash Definitions 200 */ 201 #define CONFIG_NAND_FSL_IFC 202 203 #define CONFIG_SYS_NAND_BASE 0x7e800000 204 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 205 206 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 207 208 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 209 | CSPR_PORT_SIZE_8 \ 210 | CSPR_MSEL_NAND \ 211 | CSPR_V) 212 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 213 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 214 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 215 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 216 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 217 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 218 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 219 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 220 221 #define CONFIG_SYS_NAND_ONFI_DETECTION 222 223 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 224 FTIM0_NAND_TWP(0x18) | \ 225 FTIM0_NAND_TWCHT(0x7) | \ 226 FTIM0_NAND_TWH(0xa)) 227 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 228 FTIM1_NAND_TWBE(0x39) | \ 229 FTIM1_NAND_TRR(0xe) | \ 230 FTIM1_NAND_TRP(0x18)) 231 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 232 FTIM2_NAND_TREH(0xa) | \ 233 FTIM2_NAND_TWHRE(0x1e)) 234 #define CONFIG_SYS_NAND_FTIM3 0x0 235 236 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 237 #define CONFIG_SYS_MAX_NAND_DEVICE 1 238 #define CONFIG_CMD_NAND 239 240 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 241 #endif 242 243 /* 244 * QIXIS Definitions 245 */ 246 #define CONFIG_FSL_QIXIS 247 248 #ifdef CONFIG_FSL_QIXIS 249 #define QIXIS_BASE 0x7fb00000 250 #define QIXIS_BASE_PHYS QIXIS_BASE 251 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 252 #define QIXIS_LBMAP_SWITCH 6 253 #define QIXIS_LBMAP_MASK 0x0f 254 #define QIXIS_LBMAP_SHIFT 0 255 #define QIXIS_LBMAP_DFLTBANK 0x00 256 #define QIXIS_LBMAP_ALTBANK 0x04 257 #define QIXIS_PWR_CTL 0x21 258 #define QIXIS_PWR_CTL_POWEROFF 0x80 259 #define QIXIS_RST_CTL_RESET 0x44 260 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 261 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 262 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 263 #define QIXIS_CTL_SYS 0x5 264 #define QIXIS_CTL_SYS_EVTSW_MASK 0x0c 265 #define QIXIS_CTL_SYS_EVTSW_IRQ 0x04 266 #define QIXIS_RST_FORCE_3 0x45 267 #define QIXIS_RST_FORCE_3_PCIESLOT1 0x80 268 #define QIXIS_PWR_CTL2 0x21 269 #define QIXIS_PWR_CTL2_PCTL 0x2 270 271 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 272 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 273 CSPR_PORT_SIZE_8 | \ 274 CSPR_MSEL_GPCM | \ 275 CSPR_V) 276 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 277 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 278 CSOR_NOR_NOR_MODE_AVD_NOR | \ 279 CSOR_NOR_TRHZ_80) 280 281 /* 282 * QIXIS Timing parameters for IFC GPCM 283 */ 284 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \ 285 FTIM0_GPCM_TEADC(0xe) | \ 286 FTIM0_GPCM_TEAHC(0xe)) 287 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \ 288 FTIM1_GPCM_TRAD(0x1f)) 289 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \ 290 FTIM2_GPCM_TCH(0xe) | \ 291 FTIM2_GPCM_TWP(0xf0)) 292 #define CONFIG_SYS_FPGA_FTIM3 0x0 293 #endif 294 295 #if defined(CONFIG_NAND_BOOT) 296 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 297 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 298 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 299 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 300 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 301 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 302 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 303 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 304 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 305 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 306 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 307 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 308 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 309 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 310 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 311 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 312 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 313 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 314 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 315 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 316 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 317 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 318 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 319 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 320 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 321 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 322 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 323 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 324 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 325 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 326 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 327 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 328 #else 329 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 330 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 331 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 332 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 333 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 334 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 335 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 336 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 337 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 338 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 339 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 340 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 341 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 342 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 343 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 344 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 345 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 346 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 347 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 348 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 349 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 350 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 351 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 352 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 353 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 354 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 355 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 356 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 357 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 358 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 359 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 360 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 361 #endif 362 363 /* 364 * Serial Port 365 */ 366 #ifdef CONFIG_LPUART 367 #define CONFIG_LPUART_32B_REG 368 #else 369 #define CONFIG_CONS_INDEX 1 370 #define CONFIG_SYS_NS16550_SERIAL 371 #ifndef CONFIG_DM_SERIAL 372 #define CONFIG_SYS_NS16550_REG_SIZE 1 373 #endif 374 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 375 #endif 376 377 #define CONFIG_BAUDRATE 115200 378 379 /* 380 * I2C 381 */ 382 #define CONFIG_SYS_I2C 383 #define CONFIG_SYS_I2C_MXC 384 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 385 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 386 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 387 388 /* 389 * I2C bus multiplexer 390 */ 391 #define I2C_MUX_PCA_ADDR_PRI 0x77 392 #define I2C_MUX_CH_DEFAULT 0x8 393 #define I2C_MUX_CH_CH7301 0xC 394 395 /* 396 * MMC 397 */ 398 #define CONFIG_MMC 399 #define CONFIG_FSL_ESDHC 400 #define CONFIG_GENERIC_MMC 401 402 #define CONFIG_DOS_PARTITION 403 404 /* SPI */ 405 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 406 /* QSPI */ 407 #define QSPI0_AMBA_BASE 0x40000000 408 #define FSL_QSPI_FLASH_SIZE (1 << 24) 409 #define FSL_QSPI_FLASH_NUM 2 410 411 /* DSPI */ 412 413 /* DM SPI */ 414 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 415 #define CONFIG_DM_SPI_FLASH 416 #define CONFIG_SPI_FLASH_DATAFLASH 417 #endif 418 #endif 419 420 /* 421 * USB 422 */ 423 /* EHCI Support - disbaled by default */ 424 /*#define CONFIG_HAS_FSL_DR_USB*/ 425 426 #ifdef CONFIG_HAS_FSL_DR_USB 427 #define CONFIG_USB_EHCI 428 #define CONFIG_USB_EHCI_FSL 429 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 430 #endif 431 432 /*XHCI Support - enabled by default*/ 433 #define CONFIG_HAS_FSL_XHCI_USB 434 435 #ifdef CONFIG_HAS_FSL_XHCI_USB 436 #define CONFIG_USB_XHCI_FSL 437 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 438 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 439 #endif 440 441 /* 442 * Video 443 */ 444 #define CONFIG_FSL_DCU_FB 445 446 #ifdef CONFIG_FSL_DCU_FB 447 #define CONFIG_CMD_BMP 448 #define CONFIG_VIDEO_LOGO 449 #define CONFIG_VIDEO_BMP_LOGO 450 451 #define CONFIG_FSL_DIU_CH7301 452 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0 453 #define CONFIG_SYS_I2C_QIXIS_ADDR 0x66 454 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 455 #endif 456 457 /* 458 * eTSEC 459 */ 460 #define CONFIG_TSEC_ENET 461 462 #ifdef CONFIG_TSEC_ENET 463 #define CONFIG_MII 464 #define CONFIG_MII_DEFAULT_TSEC 3 465 #define CONFIG_TSEC1 1 466 #define CONFIG_TSEC1_NAME "eTSEC1" 467 #define CONFIG_TSEC2 1 468 #define CONFIG_TSEC2_NAME "eTSEC2" 469 #define CONFIG_TSEC3 1 470 #define CONFIG_TSEC3_NAME "eTSEC3" 471 472 #define TSEC1_PHY_ADDR 1 473 #define TSEC2_PHY_ADDR 2 474 #define TSEC3_PHY_ADDR 3 475 476 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 477 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 478 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 479 480 #define TSEC1_PHYIDX 0 481 #define TSEC2_PHYIDX 0 482 #define TSEC3_PHYIDX 0 483 484 #define CONFIG_ETHPRIME "eTSEC1" 485 486 #define CONFIG_PHY_GIGE 487 #define CONFIG_PHYLIB 488 #define CONFIG_PHY_REALTEK 489 490 #define CONFIG_HAS_ETH0 491 #define CONFIG_HAS_ETH1 492 #define CONFIG_HAS_ETH2 493 494 #define CONFIG_FSL_SGMII_RISER 1 495 #define SGMII_RISER_PHY_OFFSET 0x1b 496 497 #ifdef CONFIG_FSL_SGMII_RISER 498 #define CONFIG_SYS_TBIPA_VALUE 8 499 #endif 500 501 #endif 502 503 /* PCIe */ 504 #define CONFIG_PCIE1 /* PCIE controller 1 */ 505 #define CONFIG_PCIE2 /* PCIE controller 2 */ 506 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 507 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" 508 509 #define CONFIG_SYS_PCI_64BIT 510 511 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 512 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ 513 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 514 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ 515 516 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 517 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 518 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ 519 520 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 521 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 522 #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ 523 524 #ifdef CONFIG_PCI 525 #define CONFIG_PCI_SCAN_SHOW 526 #define CONFIG_CMD_PCI 527 #endif 528 529 #define CONFIG_CMDLINE_TAG 530 #define CONFIG_CMDLINE_EDITING 531 532 #define CONFIG_PEN_ADDR_BIG_ENDIAN 533 #define CONFIG_LAYERSCAPE_NS_ACCESS 534 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 535 #define CONFIG_TIMER_CLK_FREQ 12500000 536 537 #define CONFIG_HWCONFIG 538 #define HWCONFIG_BUFFER_SIZE 256 539 540 #define CONFIG_FSL_DEVICE_DISABLE 541 542 543 #define CONFIG_SYS_QE_FW_ADDR 0x600c0000 544 545 #ifdef CONFIG_LPUART 546 #define CONFIG_EXTRA_ENV_SETTINGS \ 547 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ 548 "fdt_high=0xffffffff\0" \ 549 "initrd_high=0xffffffff\0" \ 550 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 551 #else 552 #define CONFIG_EXTRA_ENV_SETTINGS \ 553 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 554 "fdt_high=0xffffffff\0" \ 555 "initrd_high=0xffffffff\0" \ 556 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 557 #endif 558 559 /* 560 * Miscellaneous configurable options 561 */ 562 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 563 #define CONFIG_AUTO_COMPLETE 564 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 565 #define CONFIG_SYS_PBSIZE \ 566 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 567 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 568 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 569 570 #define CONFIG_SYS_MEMTEST_START 0x80000000 571 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 572 573 #define CONFIG_SYS_LOAD_ADDR 0x82000000 574 575 #define CONFIG_LS102XA_STREAM_ID 576 577 /* 578 * Stack sizes 579 * The stack sizes are set up in start.S using the settings below 580 */ 581 #define CONFIG_STACKSIZE (30 * 1024) 582 583 #define CONFIG_SYS_INIT_SP_OFFSET \ 584 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 585 #define CONFIG_SYS_INIT_SP_ADDR \ 586 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 587 588 #ifdef CONFIG_SPL_BUILD 589 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 590 #else 591 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 592 #endif 593 594 /* 595 * Environment 596 */ 597 #define CONFIG_ENV_OVERWRITE 598 599 #if defined(CONFIG_SD_BOOT) 600 #define CONFIG_ENV_OFFSET 0x100000 601 #define CONFIG_ENV_IS_IN_MMC 602 #define CONFIG_SYS_MMC_ENV_DEV 0 603 #define CONFIG_ENV_SIZE 0x2000 604 #elif defined(CONFIG_QSPI_BOOT) 605 #define CONFIG_ENV_IS_IN_SPI_FLASH 606 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 607 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 608 #define CONFIG_ENV_SECT_SIZE 0x10000 609 #elif defined(CONFIG_NAND_BOOT) 610 #define CONFIG_ENV_IS_IN_NAND 611 #define CONFIG_ENV_SIZE 0x2000 612 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 613 #else 614 #define CONFIG_ENV_IS_IN_FLASH 615 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 616 #define CONFIG_ENV_SIZE 0x2000 617 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 618 #endif 619 620 #define CONFIG_MISC_INIT_R 621 622 /* Hash command with SHA acceleration supported in hardware */ 623 #ifdef CONFIG_FSL_CAAM 624 #define CONFIG_CMD_HASH 625 #define CONFIG_SHA_HW_ACCEL 626 #endif 627 628 #include <asm/fsl_secure_boot.h> 629 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 630 631 #endif 632