xref: /openbmc/u-boot/include/configs/ls1021aqds.h (revision 5473f245)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2014 Freescale Semiconductor, Inc.
4  */
5 
6 #ifndef __CONFIG_H
7 #define __CONFIG_H
8 
9 #define CONFIG_ARMV7_PSCI_1_0
10 
11 #define CONFIG_ARMV7_SECURE_BASE	OCRAM_BASE_S_ADDR
12 
13 #define CONFIG_SYS_FSL_CLK
14 
15 #define CONFIG_SKIP_LOWLEVEL_INIT
16 
17 #define CONFIG_DEEP_SLEEP
18 
19 /*
20  * Size of malloc() pool
21  */
22 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 16 * 1024 * 1024)
23 
24 #define CONFIG_SYS_INIT_RAM_ADDR	OCRAM_BASE_ADDR
25 #define CONFIG_SYS_INIT_RAM_SIZE	OCRAM_SIZE
26 
27 #ifndef __ASSEMBLY__
28 unsigned long get_board_sys_clk(void);
29 unsigned long get_board_ddr_clk(void);
30 #endif
31 
32 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
33 #define CONFIG_SYS_CLK_FREQ		100000000
34 #define CONFIG_DDR_CLK_FREQ		100000000
35 #define CONFIG_QIXIS_I2C_ACCESS
36 #else
37 #define CONFIG_SYS_CLK_FREQ		get_board_sys_clk()
38 #define CONFIG_DDR_CLK_FREQ		get_board_ddr_clk()
39 #endif
40 
41 #ifdef CONFIG_RAMBOOT_PBL
42 #define CONFIG_SYS_FSL_PBL_PBI	board/freescale/ls1021aqds/ls102xa_pbi.cfg
43 #endif
44 
45 #ifdef CONFIG_SD_BOOT
46 #ifdef CONFIG_SD_BOOT_QSPI
47 #define CONFIG_SYS_FSL_PBL_RCW	\
48 	board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg
49 #else
50 #define CONFIG_SYS_FSL_PBL_RCW	\
51 	board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg
52 #endif
53 
54 #define CONFIG_SPL_TEXT_BASE		0x10000000
55 #define CONFIG_SPL_MAX_SIZE		0x1a000
56 #define CONFIG_SPL_STACK		0x1001d000
57 #define CONFIG_SPL_PAD_TO		0x1c000
58 
59 #define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_TEXT_BASE + \
60 		CONFIG_SYS_MONITOR_LEN)
61 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
62 #define CONFIG_SPL_BSS_START_ADDR	0x80100000
63 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000
64 #define CONFIG_SYS_MONITOR_LEN		0xc0000
65 #endif
66 
67 #ifdef CONFIG_NAND_BOOT
68 #define CONFIG_SYS_FSL_PBL_RCW	board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
69 
70 #define CONFIG_SPL_TEXT_BASE		0x10000000
71 #define CONFIG_SPL_MAX_SIZE		0x1a000
72 #define CONFIG_SPL_STACK		0x1001d000
73 #define CONFIG_SPL_PAD_TO		0x1c000
74 
75 #define CONFIG_SYS_NAND_U_BOOT_SIZE	(400 << 10)
76 #define CONFIG_SYS_NAND_U_BOOT_OFFS	CONFIG_SPL_PAD_TO
77 #define CONFIG_SYS_NAND_PAGE_SIZE	2048
78 #define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
79 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
80 
81 #define CONFIG_SYS_SPL_MALLOC_START	0x80200000
82 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
83 #define CONFIG_SPL_BSS_START_ADDR	0x80100000
84 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000
85 #define CONFIG_SYS_MONITOR_LEN		0x80000
86 #endif
87 
88 #define CONFIG_DDR_SPD
89 #define SPD_EEPROM_ADDRESS		0x51
90 #define CONFIG_SYS_SPD_BUS_NUM		0
91 
92 #define CONFIG_FSL_DDR_INTERACTIVE	/* Interactive debugging */
93 #ifndef CONFIG_SYS_FSL_DDR4
94 #define CONFIG_SYS_DDR_RAW_TIMING
95 #endif
96 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
97 #define CONFIG_CHIP_SELECTS_PER_CTRL	4
98 
99 #define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000UL
100 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
101 
102 #define CONFIG_DDR_ECC
103 #ifdef CONFIG_DDR_ECC
104 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
105 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
106 #endif
107 
108 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
109 	!defined(CONFIG_QSPI_BOOT)
110 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
111 #endif
112 
113 /*
114  * IFC Definitions
115  */
116 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
117 #define CONFIG_FSL_IFC
118 #define CONFIG_SYS_FLASH_BASE		0x60000000
119 #define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
120 
121 #define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
122 #define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
123 				CSPR_PORT_SIZE_16 | \
124 				CSPR_MSEL_NOR | \
125 				CSPR_V)
126 #define CONFIG_SYS_NOR1_CSPR_EXT	(0x0)
127 #define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
128 				+ 0x8000000) | \
129 				CSPR_PORT_SIZE_16 | \
130 				CSPR_MSEL_NOR | \
131 				CSPR_V)
132 #define CONFIG_SYS_NOR_AMASK		IFC_AMASK(128 * 1024 * 1024)
133 
134 #define CONFIG_SYS_NOR_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
135 					CSOR_NOR_TRHZ_80)
136 #define CONFIG_SYS_NOR_FTIM0		(FTIM0_NOR_TACSE(0x4) | \
137 					FTIM0_NOR_TEADC(0x5) | \
138 					FTIM0_NOR_TEAHC(0x5))
139 #define CONFIG_SYS_NOR_FTIM1		(FTIM1_NOR_TACO(0x35) | \
140 					FTIM1_NOR_TRAD_NOR(0x1a) | \
141 					FTIM1_NOR_TSEQRAD_NOR(0x13))
142 #define CONFIG_SYS_NOR_FTIM2		(FTIM2_NOR_TCS(0x4) | \
143 					FTIM2_NOR_TCH(0x4) | \
144 					FTIM2_NOR_TWPH(0xe) | \
145 					FTIM2_NOR_TWP(0x1c))
146 #define CONFIG_SYS_NOR_FTIM3		0
147 
148 #define CONFIG_SYS_FLASH_QUIET_TEST
149 #define CONFIG_FLASH_SHOW_PROGRESS	45
150 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
151 #define CONFIG_SYS_WRITE_SWAPPED_DATA
152 
153 #define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
154 #define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
155 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
156 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
157 
158 #define CONFIG_SYS_FLASH_EMPTY_INFO
159 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS, \
160 					CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
161 
162 /*
163  * NAND Flash Definitions
164  */
165 #define CONFIG_NAND_FSL_IFC
166 
167 #define CONFIG_SYS_NAND_BASE		0x7e800000
168 #define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
169 
170 #define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
171 
172 #define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
173 				| CSPR_PORT_SIZE_8	\
174 				| CSPR_MSEL_NAND	\
175 				| CSPR_V)
176 #define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
177 #define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
178 				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
179 				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */ \
180 				| CSOR_NAND_RAL_3	/* RAL = 3 Bytes */ \
181 				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
182 				| CSOR_NAND_SPRZ_64	/* Spare size = 64 */ \
183 				| CSOR_NAND_PB(64))	/* 64 Pages Per Block */
184 
185 #define CONFIG_SYS_NAND_ONFI_DETECTION
186 
187 #define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x7) | \
188 					FTIM0_NAND_TWP(0x18)   | \
189 					FTIM0_NAND_TWCHT(0x7) | \
190 					FTIM0_NAND_TWH(0xa))
191 #define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
192 					FTIM1_NAND_TWBE(0x39)  | \
193 					FTIM1_NAND_TRR(0xe)   | \
194 					FTIM1_NAND_TRP(0x18))
195 #define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0xf) | \
196 					FTIM2_NAND_TREH(0xa) | \
197 					FTIM2_NAND_TWHRE(0x1e))
198 #define CONFIG_SYS_NAND_FTIM3           0x0
199 
200 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
201 #define CONFIG_SYS_MAX_NAND_DEVICE	1
202 
203 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
204 #endif
205 
206 /*
207  * QIXIS Definitions
208  */
209 #define CONFIG_FSL_QIXIS
210 
211 #ifdef CONFIG_FSL_QIXIS
212 #define QIXIS_BASE			0x7fb00000
213 #define QIXIS_BASE_PHYS			QIXIS_BASE
214 #define CONFIG_SYS_I2C_FPGA_ADDR	0x66
215 #define QIXIS_LBMAP_SWITCH		6
216 #define QIXIS_LBMAP_MASK		0x0f
217 #define QIXIS_LBMAP_SHIFT		0
218 #define QIXIS_LBMAP_DFLTBANK		0x00
219 #define QIXIS_LBMAP_ALTBANK		0x04
220 #define QIXIS_PWR_CTL			0x21
221 #define QIXIS_PWR_CTL_POWEROFF		0x80
222 #define QIXIS_RST_CTL_RESET		0x44
223 #define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
224 #define QIXIS_RCFG_CTL_RECONFIG_START	0x21
225 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
226 #define QIXIS_CTL_SYS			0x5
227 #define QIXIS_CTL_SYS_EVTSW_MASK	0x0c
228 #define QIXIS_CTL_SYS_EVTSW_IRQ		0x04
229 #define QIXIS_RST_FORCE_3		0x45
230 #define QIXIS_RST_FORCE_3_PCIESLOT1	0x80
231 #define QIXIS_PWR_CTL2			0x21
232 #define QIXIS_PWR_CTL2_PCTL		0x2
233 
234 #define CONFIG_SYS_FPGA_CSPR_EXT	(0x0)
235 #define CONFIG_SYS_FPGA_CSPR		(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
236 					CSPR_PORT_SIZE_8 | \
237 					CSPR_MSEL_GPCM | \
238 					CSPR_V)
239 #define CONFIG_SYS_FPGA_AMASK		IFC_AMASK(64 * 1024)
240 #define CONFIG_SYS_FPGA_CSOR		(CSOR_NOR_ADM_SHIFT(4) | \
241 					CSOR_NOR_NOR_MODE_AVD_NOR | \
242 					CSOR_NOR_TRHZ_80)
243 
244 /*
245  * QIXIS Timing parameters for IFC GPCM
246  */
247 #define CONFIG_SYS_FPGA_FTIM0		(FTIM0_GPCM_TACSE(0xe) | \
248 					FTIM0_GPCM_TEADC(0xe) | \
249 					FTIM0_GPCM_TEAHC(0xe))
250 #define CONFIG_SYS_FPGA_FTIM1		(FTIM1_GPCM_TACO(0xe) | \
251 					FTIM1_GPCM_TRAD(0x1f))
252 #define CONFIG_SYS_FPGA_FTIM2		(FTIM2_GPCM_TCS(0xe) | \
253 					FTIM2_GPCM_TCH(0xe) | \
254 					FTIM2_GPCM_TWP(0xf0))
255 #define CONFIG_SYS_FPGA_FTIM3		0x0
256 #endif
257 
258 #if defined(CONFIG_NAND_BOOT)
259 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
260 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
261 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
262 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
263 #define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
264 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
265 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
266 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
267 #define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
268 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
269 #define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
270 #define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
271 #define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
272 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
273 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
274 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
275 #define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
276 #define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
277 #define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
278 #define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
279 #define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
280 #define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
281 #define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
282 #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
283 #define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
284 #define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
285 #define CONFIG_SYS_AMASK3		CONFIG_SYS_FPGA_AMASK
286 #define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
287 #define CONFIG_SYS_CS3_FTIM0		CONFIG_SYS_FPGA_FTIM0
288 #define CONFIG_SYS_CS3_FTIM1		CONFIG_SYS_FPGA_FTIM1
289 #define CONFIG_SYS_CS3_FTIM2		CONFIG_SYS_FPGA_FTIM2
290 #define CONFIG_SYS_CS3_FTIM3		CONFIG_SYS_FPGA_FTIM3
291 #else
292 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
293 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
294 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
295 #define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
296 #define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
297 #define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
298 #define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
299 #define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
300 #define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
301 #define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
302 #define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
303 #define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
304 #define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
305 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
306 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
307 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
308 #define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
309 #define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
310 #define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
311 #define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
312 #define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
313 #define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
314 #define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
315 #define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
316 #define CONFIG_SYS_CSPR3_EXT		CONFIG_SYS_FPGA_CSPR_EXT
317 #define CONFIG_SYS_CSPR3		CONFIG_SYS_FPGA_CSPR
318 #define CONFIG_SYS_AMASK3		CONFIG_SYS_FPGA_AMASK
319 #define CONFIG_SYS_CSOR3		CONFIG_SYS_FPGA_CSOR
320 #define CONFIG_SYS_CS3_FTIM0		CONFIG_SYS_FPGA_FTIM0
321 #define CONFIG_SYS_CS3_FTIM1		CONFIG_SYS_FPGA_FTIM1
322 #define CONFIG_SYS_CS3_FTIM2		CONFIG_SYS_FPGA_FTIM2
323 #define CONFIG_SYS_CS3_FTIM3		CONFIG_SYS_FPGA_FTIM3
324 #endif
325 
326 /*
327  * Serial Port
328  */
329 #ifdef CONFIG_LPUART
330 #define CONFIG_LPUART_32B_REG
331 #else
332 #define CONFIG_SYS_NS16550_SERIAL
333 #ifndef CONFIG_DM_SERIAL
334 #define CONFIG_SYS_NS16550_REG_SIZE	1
335 #endif
336 #define CONFIG_SYS_NS16550_CLK		get_serial_clock()
337 #endif
338 
339 /*
340  * I2C
341  */
342 #define CONFIG_SYS_I2C
343 #define CONFIG_SYS_I2C_MXC
344 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
345 #define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
346 #define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
347 
348 /* EEPROM */
349 #define CONFIG_ID_EEPROM
350 #define CONFIG_SYS_I2C_EEPROM_NXID
351 #define CONFIG_SYS_EEPROM_BUS_NUM		0
352 #define CONFIG_SYS_I2C_EEPROM_ADDR		0x57
353 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
354 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
355 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
356 
357 /*
358  * I2C bus multiplexer
359  */
360 #define I2C_MUX_PCA_ADDR_PRI		0x77
361 #define I2C_MUX_CH_DEFAULT		0x8
362 #define I2C_MUX_CH_CH7301		0xC
363 
364 /*
365  * MMC
366  */
367 
368 /* SPI */
369 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
370 /* QSPI */
371 #define QSPI0_AMBA_BASE			0x40000000
372 #define FSL_QSPI_FLASH_SIZE		(1 << 24)
373 #define FSL_QSPI_FLASH_NUM		2
374 
375 /* DSPI */
376 
377 /* DM SPI */
378 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
379 #define CONFIG_DM_SPI_FLASH
380 #define CONFIG_SPI_FLASH_DATAFLASH
381 #endif
382 #endif
383 
384 /*
385  * Video
386  */
387 #ifdef CONFIG_VIDEO_FSL_DCU_FB
388 #define CONFIG_VIDEO_LOGO
389 #define CONFIG_VIDEO_BMP_LOGO
390 
391 #define CONFIG_FSL_DIU_CH7301
392 #define CONFIG_SYS_I2C_DVI_BUS_NUM	0
393 #define CONFIG_SYS_I2C_QIXIS_ADDR	0x66
394 #define CONFIG_SYS_I2C_DVI_ADDR		0x75
395 #endif
396 
397 /*
398  * eTSEC
399  */
400 
401 #ifdef CONFIG_TSEC_ENET
402 #define CONFIG_MII_DEFAULT_TSEC		3
403 #define CONFIG_TSEC1			1
404 #define CONFIG_TSEC1_NAME		"eTSEC1"
405 #define CONFIG_TSEC2			1
406 #define CONFIG_TSEC2_NAME		"eTSEC2"
407 #define CONFIG_TSEC3			1
408 #define CONFIG_TSEC3_NAME		"eTSEC3"
409 
410 #define TSEC1_PHY_ADDR			1
411 #define TSEC2_PHY_ADDR			2
412 #define TSEC3_PHY_ADDR			3
413 
414 #define TSEC1_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
415 #define TSEC2_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
416 #define TSEC3_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
417 
418 #define TSEC1_PHYIDX			0
419 #define TSEC2_PHYIDX			0
420 #define TSEC3_PHYIDX			0
421 
422 #define CONFIG_ETHPRIME			"eTSEC1"
423 
424 #define CONFIG_PHY_REALTEK
425 
426 #define CONFIG_HAS_ETH0
427 #define CONFIG_HAS_ETH1
428 #define CONFIG_HAS_ETH2
429 
430 #define CONFIG_FSL_SGMII_RISER		1
431 #define SGMII_RISER_PHY_OFFSET		0x1b
432 
433 #ifdef CONFIG_FSL_SGMII_RISER
434 #define CONFIG_SYS_TBIPA_VALUE		8
435 #endif
436 
437 #endif
438 
439 /* PCIe */
440 #define CONFIG_PCIE1		/* PCIE controller 1 */
441 #define CONFIG_PCIE2		/* PCIE controller 2 */
442 
443 #ifdef CONFIG_PCI
444 #define CONFIG_PCI_SCAN_SHOW
445 #endif
446 
447 #define CONFIG_CMDLINE_TAG
448 
449 #define CONFIG_PEN_ADDR_BIG_ENDIAN
450 #define CONFIG_LAYERSCAPE_NS_ACCESS
451 #define CONFIG_SMP_PEN_ADDR		0x01ee0200
452 #define COUNTER_FREQUENCY		12500000
453 
454 #define CONFIG_HWCONFIG
455 #define HWCONFIG_BUFFER_SIZE		256
456 
457 #define CONFIG_FSL_DEVICE_DISABLE
458 
459 
460 #define CONFIG_SYS_QE_FW_ADDR     0x60940000
461 
462 #ifdef CONFIG_LPUART
463 #define CONFIG_EXTRA_ENV_SETTINGS       \
464 	"bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
465 	"fdt_high=0xffffffff\0"         \
466 	"initrd_high=0xffffffff\0"      \
467 	"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
468 #else
469 #define CONFIG_EXTRA_ENV_SETTINGS	\
470 	"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
471 	"fdt_high=0xffffffff\0"		\
472 	"initrd_high=0xffffffff\0"      \
473 	"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
474 #endif
475 
476 /*
477  * Miscellaneous configurable options
478  */
479 
480 #define CONFIG_SYS_MEMTEST_START	0x80000000
481 #define CONFIG_SYS_MEMTEST_END		0x9fffffff
482 
483 #define CONFIG_SYS_LOAD_ADDR		0x82000000
484 
485 #define CONFIG_LS102XA_STREAM_ID
486 
487 #define CONFIG_SYS_INIT_SP_OFFSET \
488 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
489 #define CONFIG_SYS_INIT_SP_ADDR \
490 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
491 
492 #ifdef CONFIG_SPL_BUILD
493 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
494 #else
495 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
496 #endif
497 
498 /*
499  * Environment
500  */
501 #define CONFIG_ENV_OVERWRITE
502 
503 #if defined(CONFIG_SD_BOOT)
504 #define CONFIG_ENV_OFFSET		0x300000
505 #define CONFIG_SYS_MMC_ENV_DEV		0
506 #define CONFIG_ENV_SIZE			0x2000
507 #elif defined(CONFIG_QSPI_BOOT)
508 #define CONFIG_ENV_SIZE			0x2000          /* 8KB */
509 #define CONFIG_ENV_OFFSET		0x300000        /* 3MB */
510 #define CONFIG_ENV_SECT_SIZE		0x10000
511 #elif defined(CONFIG_NAND_BOOT)
512 #define CONFIG_ENV_SIZE			0x2000
513 #define CONFIG_ENV_OFFSET		(10 * CONFIG_SYS_NAND_BLOCK_SIZE)
514 #else
515 #define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x300000)
516 #define CONFIG_ENV_SIZE			0x2000
517 #define CONFIG_ENV_SECT_SIZE		0x20000 /* 128K (one sector) */
518 #endif
519 
520 #include <asm/fsl_secure_boot.h>
521 #define CONFIG_SYS_BOOTM_LEN	(64 << 20) /* Increase max gunzip size */
522 
523 #endif
524