1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #include <config_cmd_default.h> 11 12 #define CONFIG_LS102XA 13 14 #define CONFIG_SYS_GENERIC_BOARD 15 16 #define CONFIG_DISPLAY_CPUINFO 17 #define CONFIG_DISPLAY_BOARDINFO 18 19 #define CONFIG_SKIP_LOWLEVEL_INIT 20 #define CONFIG_BOARD_EARLY_INIT_F 21 22 /* 23 * Size of malloc() pool 24 */ 25 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 26 27 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 28 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 29 30 /* 31 * Generic Timer Definitions 32 */ 33 #define GENERIC_TIMER_CLK 12500000 34 35 #ifndef __ASSEMBLY__ 36 unsigned long get_board_sys_clk(void); 37 unsigned long get_board_ddr_clk(void); 38 #endif 39 40 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 41 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 42 43 #ifndef CONFIG_SYS_TEXT_BASE 44 #define CONFIG_SYS_TEXT_BASE 0x67f80000 45 #endif 46 47 #define CONFIG_NR_DRAM_BANKS 1 48 49 #define CONFIG_DDR_SPD 50 #define SPD_EEPROM_ADDRESS 0x51 51 #define CONFIG_SYS_SPD_BUS_NUM 0 52 #define CONFIG_SYS_DDR_RAW_TIMING 53 54 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 55 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ 56 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 57 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 58 59 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 60 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 61 62 #define CONFIG_DDR_ECC 63 #ifdef CONFIG_DDR_ECC 64 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 65 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 66 #endif 67 68 #define CONFIG_SYS_HAS_SERDES 69 70 /* 71 * IFC Definitions 72 */ 73 #define CONFIG_FSL_IFC 74 #define CONFIG_SYS_FLASH_BASE 0x60000000 75 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 76 77 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 78 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 79 CSPR_PORT_SIZE_16 | \ 80 CSPR_MSEL_NOR | \ 81 CSPR_V) 82 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 83 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 84 + 0x8000000) | \ 85 CSPR_PORT_SIZE_16 | \ 86 CSPR_MSEL_NOR | \ 87 CSPR_V) 88 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 89 90 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 91 CSOR_NOR_TRHZ_80) 92 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 93 FTIM0_NOR_TEADC(0x5) | \ 94 FTIM0_NOR_TEAHC(0x5)) 95 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 96 FTIM1_NOR_TRAD_NOR(0x1a) | \ 97 FTIM1_NOR_TSEQRAD_NOR(0x13)) 98 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 99 FTIM2_NOR_TCH(0x4) | \ 100 FTIM2_NOR_TWPH(0xe) | \ 101 FTIM2_NOR_TWP(0x1c)) 102 #define CONFIG_SYS_NOR_FTIM3 0 103 104 #define CONFIG_FLASH_CFI_DRIVER 105 #define CONFIG_SYS_FLASH_CFI 106 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 107 #define CONFIG_SYS_FLASH_QUIET_TEST 108 #define CONFIG_FLASH_SHOW_PROGRESS 45 109 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 110 111 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 112 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 113 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 114 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 115 116 #define CONFIG_SYS_FLASH_EMPTY_INFO 117 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 118 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 119 120 /* 121 * NAND Flash Definitions 122 */ 123 #define CONFIG_NAND_FSL_IFC 124 125 #define CONFIG_SYS_NAND_BASE 0x7e800000 126 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 127 128 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 129 130 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 131 | CSPR_PORT_SIZE_8 \ 132 | CSPR_MSEL_NAND \ 133 | CSPR_V) 134 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 135 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 136 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 137 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 138 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 139 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 140 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 141 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 142 143 #define CONFIG_SYS_NAND_ONFI_DETECTION 144 145 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 146 FTIM0_NAND_TWP(0x18) | \ 147 FTIM0_NAND_TWCHT(0x7) | \ 148 FTIM0_NAND_TWH(0xa)) 149 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 150 FTIM1_NAND_TWBE(0x39) | \ 151 FTIM1_NAND_TRR(0xe) | \ 152 FTIM1_NAND_TRP(0x18)) 153 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 154 FTIM2_NAND_TREH(0xa) | \ 155 FTIM2_NAND_TWHRE(0x1e)) 156 #define CONFIG_SYS_NAND_FTIM3 0x0 157 158 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 159 #define CONFIG_SYS_MAX_NAND_DEVICE 1 160 #define CONFIG_MTD_NAND_VERIFY_WRITE 161 #define CONFIG_CMD_NAND 162 163 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 164 165 /* 166 * QIXIS Definitions 167 */ 168 #define CONFIG_FSL_QIXIS 169 170 #ifdef CONFIG_FSL_QIXIS 171 #define QIXIS_BASE 0x7fb00000 172 #define QIXIS_BASE_PHYS QIXIS_BASE 173 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 174 #define QIXIS_LBMAP_SWITCH 6 175 #define QIXIS_LBMAP_MASK 0x0f 176 #define QIXIS_LBMAP_SHIFT 0 177 #define QIXIS_LBMAP_DFLTBANK 0x00 178 #define QIXIS_LBMAP_ALTBANK 0x04 179 #define QIXIS_RST_CTL_RESET 0x44 180 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 181 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 182 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 183 184 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 185 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 186 CSPR_PORT_SIZE_8 | \ 187 CSPR_MSEL_GPCM | \ 188 CSPR_V) 189 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 190 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 191 CSOR_NOR_NOR_MODE_AVD_NOR | \ 192 CSOR_NOR_TRHZ_80) 193 194 /* 195 * QIXIS Timing parameters for IFC GPCM 196 */ 197 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \ 198 FTIM0_GPCM_TEADC(0xe) | \ 199 FTIM0_GPCM_TEAHC(0xe)) 200 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \ 201 FTIM1_GPCM_TRAD(0x1f)) 202 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \ 203 FTIM2_GPCM_TCH(0xe) | \ 204 FTIM2_GPCM_TWP(0xf0)) 205 #define CONFIG_SYS_FPGA_FTIM3 0x0 206 #endif 207 208 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 209 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 210 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 211 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 212 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 213 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 214 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 215 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 216 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 217 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 218 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 219 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 220 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 221 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 222 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 223 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 224 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 225 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 226 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 227 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 228 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 229 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 230 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 231 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 232 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 233 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 234 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 235 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 236 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 237 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 238 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 239 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 240 241 /* 242 * Serial Port 243 */ 244 #define CONFIG_CONS_INDEX 1 245 #define CONFIG_SYS_NS16550 246 #define CONFIG_SYS_NS16550_SERIAL 247 #define CONFIG_SYS_NS16550_REG_SIZE 1 248 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 249 250 #define CONFIG_BAUDRATE 115200 251 252 /* 253 * I2C 254 */ 255 #define CONFIG_CMD_I2C 256 #define CONFIG_SYS_I2C 257 #define CONFIG_SYS_I2C_MXC 258 259 /* 260 * I2C bus multiplexer 261 */ 262 #define I2C_MUX_PCA_ADDR_PRI 0x77 263 #define I2C_MUX_CH_DEFAULT 0x8 264 265 /* 266 * MMC 267 */ 268 #define CONFIG_MMC 269 #define CONFIG_CMD_MMC 270 #define CONFIG_FSL_ESDHC 271 #define CONFIG_GENERIC_MMC 272 273 /* 274 * eTSEC 275 */ 276 #define CONFIG_TSEC_ENET 277 278 #ifdef CONFIG_TSEC_ENET 279 #define CONFIG_MII 280 #define CONFIG_MII_DEFAULT_TSEC 3 281 #define CONFIG_TSEC1 1 282 #define CONFIG_TSEC1_NAME "eTSEC1" 283 #define CONFIG_TSEC2 1 284 #define CONFIG_TSEC2_NAME "eTSEC2" 285 #define CONFIG_TSEC3 1 286 #define CONFIG_TSEC3_NAME "eTSEC3" 287 288 #define TSEC1_PHY_ADDR 1 289 #define TSEC2_PHY_ADDR 2 290 #define TSEC3_PHY_ADDR 3 291 292 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 293 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 294 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 295 296 #define TSEC1_PHYIDX 0 297 #define TSEC2_PHYIDX 0 298 #define TSEC3_PHYIDX 0 299 300 #define CONFIG_ETHPRIME "eTSEC1" 301 302 #define CONFIG_PHY_GIGE 303 #define CONFIG_PHYLIB 304 #define CONFIG_PHY_REALTEK 305 306 #define CONFIG_HAS_ETH0 307 #define CONFIG_HAS_ETH1 308 #define CONFIG_HAS_ETH2 309 310 #define CONFIG_FSL_SGMII_RISER 1 311 #define SGMII_RISER_PHY_OFFSET 0x1b 312 313 #ifdef CONFIG_FSL_SGMII_RISER 314 #define CONFIG_SYS_TBIPA_VALUE 8 315 #endif 316 317 #endif 318 #define CONFIG_CMD_PING 319 #define CONFIG_CMD_DHCP 320 #define CONFIG_CMD_MII 321 #define CONFIG_CMD_NET 322 323 #define CONFIG_CMDLINE_TAG 324 #define CONFIG_CMDLINE_EDITING 325 #define CONFIG_CMD_IMLS 326 327 #define CONFIG_HWCONFIG 328 #define HWCONFIG_BUFFER_SIZE 128 329 330 #define CONFIG_BOOTDELAY 3 331 332 #define CONFIG_EXTRA_ENV_SETTINGS \ 333 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 334 "fdt_high=0xcfffffff\0" \ 335 "initrd_high=0xcfffffff\0" \ 336 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 337 338 /* 339 * Miscellaneous configurable options 340 */ 341 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 342 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 343 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 344 #define CONFIG_SYS_PROMPT "=> " 345 #define CONFIG_AUTO_COMPLETE 346 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 347 #define CONFIG_SYS_PBSIZE \ 348 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 349 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 350 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 351 352 #define CONFIG_CMD_ENV_EXISTS 353 #define CONFIG_CMD_GREPENV 354 #define CONFIG_CMD_MEMINFO 355 #define CONFIG_CMD_MEMTEST 356 #define CONFIG_SYS_MEMTEST_START 0x80000000 357 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 358 359 #define CONFIG_SYS_LOAD_ADDR 0x82000000 360 #define CONFIG_SYS_HZ 1000 361 362 /* 363 * Stack sizes 364 * The stack sizes are set up in start.S using the settings below 365 */ 366 #define CONFIG_STACKSIZE (30 * 1024) 367 368 #define CONFIG_SYS_INIT_SP_OFFSET \ 369 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 370 #define CONFIG_SYS_INIT_SP_ADDR \ 371 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 372 373 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 374 375 /* 376 * Environment 377 */ 378 #define CONFIG_ENV_OVERWRITE 379 380 #define CONFIG_ENV_IS_IN_FLASH 381 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 382 #define CONFIG_ENV_SIZE 0x2000 383 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 384 385 #define CONFIG_OF_LIBFDT 386 #define CONFIG_OF_BOARD_SETUP 387 #define CONFIG_CMD_BOOTZ 388 389 #endif 390