1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #include <config_cmd_default.h> 11 12 #define CONFIG_LS102XA 13 14 #define CONFIG_SYS_GENERIC_BOARD 15 16 #define CONFIG_DISPLAY_CPUINFO 17 #define CONFIG_DISPLAY_BOARDINFO 18 19 #define CONFIG_SKIP_LOWLEVEL_INIT 20 #define CONFIG_BOARD_EARLY_INIT_F 21 22 #define CONFIG_DEEP_SLEEP 23 #if defined(CONFIG_DEEP_SLEEP) 24 #define CONFIG_SILENT_CONSOLE 25 #endif 26 27 /* 28 * Size of malloc() pool 29 */ 30 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 31 32 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 33 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 34 35 /* 36 * Generic Timer Definitions 37 */ 38 #define GENERIC_TIMER_CLK 12500000 39 40 #ifndef __ASSEMBLY__ 41 unsigned long get_board_sys_clk(void); 42 unsigned long get_board_ddr_clk(void); 43 #endif 44 45 #ifdef CONFIG_QSPI_BOOT 46 #define CONFIG_SYS_CLK_FREQ 100000000 47 #define CONFIG_DDR_CLK_FREQ 100000000 48 #define CONFIG_QIXIS_I2C_ACCESS 49 #else 50 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 51 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 52 #endif 53 54 #ifdef CONFIG_RAMBOOT_PBL 55 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg 56 #endif 57 58 #ifdef CONFIG_SD_BOOT 59 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg 60 #define CONFIG_SPL_FRAMEWORK 61 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 62 #define CONFIG_SPL_LIBCOMMON_SUPPORT 63 #define CONFIG_SPL_LIBGENERIC_SUPPORT 64 #define CONFIG_SPL_ENV_SUPPORT 65 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 66 #define CONFIG_SPL_I2C_SUPPORT 67 #define CONFIG_SPL_WATCHDOG_SUPPORT 68 #define CONFIG_SPL_SERIAL_SUPPORT 69 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 70 #define CONFIG_SPL_MMC_SUPPORT 71 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 72 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 73 74 #define CONFIG_SPL_TEXT_BASE 0x10000000 75 #define CONFIG_SPL_MAX_SIZE 0x1a000 76 #define CONFIG_SPL_STACK 0x1001d000 77 #define CONFIG_SPL_PAD_TO 0x1c000 78 #define CONFIG_SYS_TEXT_BASE 0x82000000 79 80 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 81 CONFIG_SYS_MONITOR_LEN) 82 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 83 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 84 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 85 #define CONFIG_SYS_MONITOR_LEN 0x80000 86 #endif 87 88 #ifdef CONFIG_QSPI_BOOT 89 #define CONFIG_SYS_TEXT_BASE 0x40010000 90 #define CONFIG_SYS_NO_FLASH 91 #endif 92 93 #ifdef CONFIG_NAND_BOOT 94 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg 95 #define CONFIG_SPL_FRAMEWORK 96 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 97 #define CONFIG_SPL_LIBCOMMON_SUPPORT 98 #define CONFIG_SPL_LIBGENERIC_SUPPORT 99 #define CONFIG_SPL_ENV_SUPPORT 100 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 101 #define CONFIG_SPL_I2C_SUPPORT 102 #define CONFIG_SPL_WATCHDOG_SUPPORT 103 #define CONFIG_SPL_SERIAL_SUPPORT 104 #define CONFIG_SPL_NAND_SUPPORT 105 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT 106 107 #define CONFIG_SPL_TEXT_BASE 0x10000000 108 #define CONFIG_SPL_MAX_SIZE 0x1a000 109 #define CONFIG_SPL_STACK 0x1001d000 110 #define CONFIG_SPL_PAD_TO 0x1c000 111 #define CONFIG_SYS_TEXT_BASE 0x82000000 112 113 #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10) 114 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 115 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 116 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 117 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 118 119 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 120 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 121 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 122 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 123 #define CONFIG_SYS_MONITOR_LEN 0x80000 124 #endif 125 126 #ifndef CONFIG_SYS_TEXT_BASE 127 #define CONFIG_SYS_TEXT_BASE 0x67f80000 128 #endif 129 130 #define CONFIG_NR_DRAM_BANKS 1 131 132 #define CONFIG_DDR_SPD 133 #define SPD_EEPROM_ADDRESS 0x51 134 #define CONFIG_SYS_SPD_BUS_NUM 0 135 136 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 137 #ifndef CONFIG_SYS_FSL_DDR4 138 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ 139 #define CONFIG_SYS_DDR_RAW_TIMING 140 #endif 141 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 142 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 143 144 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 145 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 146 147 #define CONFIG_DDR_ECC 148 #ifdef CONFIG_DDR_ECC 149 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 150 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 151 #endif 152 153 #define CONFIG_SYS_HAS_SERDES 154 155 #define CONFIG_FSL_CAAM /* Enable CAAM */ 156 157 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ 158 !defined(CONFIG_QSPI_BOOT) 159 #define CONFIG_U_QE 160 #endif 161 162 /* 163 * IFC Definitions 164 */ 165 #ifndef CONFIG_QSPI_BOOT 166 #define CONFIG_FSL_IFC 167 #define CONFIG_SYS_FLASH_BASE 0x60000000 168 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 169 170 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 171 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 172 CSPR_PORT_SIZE_16 | \ 173 CSPR_MSEL_NOR | \ 174 CSPR_V) 175 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 176 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 177 + 0x8000000) | \ 178 CSPR_PORT_SIZE_16 | \ 179 CSPR_MSEL_NOR | \ 180 CSPR_V) 181 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 182 183 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 184 CSOR_NOR_TRHZ_80) 185 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 186 FTIM0_NOR_TEADC(0x5) | \ 187 FTIM0_NOR_TEAHC(0x5)) 188 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 189 FTIM1_NOR_TRAD_NOR(0x1a) | \ 190 FTIM1_NOR_TSEQRAD_NOR(0x13)) 191 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 192 FTIM2_NOR_TCH(0x4) | \ 193 FTIM2_NOR_TWPH(0xe) | \ 194 FTIM2_NOR_TWP(0x1c)) 195 #define CONFIG_SYS_NOR_FTIM3 0 196 197 #define CONFIG_FLASH_CFI_DRIVER 198 #define CONFIG_SYS_FLASH_CFI 199 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 200 #define CONFIG_SYS_FLASH_QUIET_TEST 201 #define CONFIG_FLASH_SHOW_PROGRESS 45 202 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 203 #define CONFIG_SYS_WRITE_SWAPPED_DATA 204 205 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 206 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 207 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 208 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 209 210 #define CONFIG_SYS_FLASH_EMPTY_INFO 211 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 212 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 213 214 /* 215 * NAND Flash Definitions 216 */ 217 #define CONFIG_NAND_FSL_IFC 218 219 #define CONFIG_SYS_NAND_BASE 0x7e800000 220 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 221 222 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 223 224 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 225 | CSPR_PORT_SIZE_8 \ 226 | CSPR_MSEL_NAND \ 227 | CSPR_V) 228 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 229 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 230 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 231 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 232 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 233 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 234 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 235 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 236 237 #define CONFIG_SYS_NAND_ONFI_DETECTION 238 239 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 240 FTIM0_NAND_TWP(0x18) | \ 241 FTIM0_NAND_TWCHT(0x7) | \ 242 FTIM0_NAND_TWH(0xa)) 243 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 244 FTIM1_NAND_TWBE(0x39) | \ 245 FTIM1_NAND_TRR(0xe) | \ 246 FTIM1_NAND_TRP(0x18)) 247 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 248 FTIM2_NAND_TREH(0xa) | \ 249 FTIM2_NAND_TWHRE(0x1e)) 250 #define CONFIG_SYS_NAND_FTIM3 0x0 251 252 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 253 #define CONFIG_SYS_MAX_NAND_DEVICE 1 254 #define CONFIG_MTD_NAND_VERIFY_WRITE 255 #define CONFIG_CMD_NAND 256 257 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 258 #endif 259 260 /* 261 * QIXIS Definitions 262 */ 263 #define CONFIG_FSL_QIXIS 264 265 #ifdef CONFIG_FSL_QIXIS 266 #define QIXIS_BASE 0x7fb00000 267 #define QIXIS_BASE_PHYS QIXIS_BASE 268 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 269 #define QIXIS_LBMAP_SWITCH 6 270 #define QIXIS_LBMAP_MASK 0x0f 271 #define QIXIS_LBMAP_SHIFT 0 272 #define QIXIS_LBMAP_DFLTBANK 0x00 273 #define QIXIS_LBMAP_ALTBANK 0x04 274 #define QIXIS_RST_CTL_RESET 0x44 275 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 276 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 277 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 278 279 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 280 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 281 CSPR_PORT_SIZE_8 | \ 282 CSPR_MSEL_GPCM | \ 283 CSPR_V) 284 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 285 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 286 CSOR_NOR_NOR_MODE_AVD_NOR | \ 287 CSOR_NOR_TRHZ_80) 288 289 /* 290 * QIXIS Timing parameters for IFC GPCM 291 */ 292 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \ 293 FTIM0_GPCM_TEADC(0xe) | \ 294 FTIM0_GPCM_TEAHC(0xe)) 295 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \ 296 FTIM1_GPCM_TRAD(0x1f)) 297 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \ 298 FTIM2_GPCM_TCH(0xe) | \ 299 FTIM2_GPCM_TWP(0xf0)) 300 #define CONFIG_SYS_FPGA_FTIM3 0x0 301 #endif 302 303 #if defined(CONFIG_NAND_BOOT) 304 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 305 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 306 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 307 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 308 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 309 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 310 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 311 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 312 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 313 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 314 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 315 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 316 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 317 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 318 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 319 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 320 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 321 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 322 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 323 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 324 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 325 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 326 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 327 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 328 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 329 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 330 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 331 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 332 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 333 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 334 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 335 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 336 #else 337 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 338 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 339 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 340 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 341 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 342 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 343 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 344 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 345 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 346 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 347 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 348 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 349 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 350 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 351 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 352 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 353 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 354 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 355 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 356 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 357 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 358 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 359 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 360 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 361 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 362 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 363 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 364 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 365 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 366 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 367 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 368 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 369 #endif 370 371 /* 372 * Serial Port 373 */ 374 #ifdef CONFIG_LPUART 375 #define CONFIG_FSL_LPUART 376 #define CONFIG_LPUART_32B_REG 377 #else 378 #define CONFIG_CONS_INDEX 1 379 #define CONFIG_SYS_NS16550 380 #define CONFIG_SYS_NS16550_SERIAL 381 #define CONFIG_SYS_NS16550_REG_SIZE 1 382 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 383 #endif 384 385 #define CONFIG_BAUDRATE 115200 386 387 /* 388 * I2C 389 */ 390 #define CONFIG_CMD_I2C 391 #define CONFIG_SYS_I2C 392 #define CONFIG_SYS_I2C_MXC 393 394 /* 395 * I2C bus multiplexer 396 */ 397 #define I2C_MUX_PCA_ADDR_PRI 0x77 398 #define I2C_MUX_CH_DEFAULT 0x8 399 #define I2C_MUX_CH_CH7301 0xC 400 401 /* 402 * MMC 403 */ 404 #define CONFIG_MMC 405 #define CONFIG_CMD_MMC 406 #define CONFIG_FSL_ESDHC 407 #define CONFIG_GENERIC_MMC 408 409 #define CONFIG_CMD_FAT 410 #define CONFIG_DOS_PARTITION 411 412 /* QSPI */ 413 #ifdef CONFIG_QSPI_BOOT 414 #define CONFIG_FSL_QSPI 415 #define QSPI0_AMBA_BASE 0x40000000 416 #define FSL_QSPI_FLASH_SIZE (1 << 24) 417 #define FSL_QSPI_FLASH_NUM 2 418 419 #define CONFIG_CMD_SF 420 #define CONFIG_SPI_FLASH 421 #define CONFIG_SPI_FLASH_SPANSION 422 #endif 423 424 /* 425 * USB 426 */ 427 #define CONFIG_HAS_FSL_DR_USB 428 429 #ifdef CONFIG_HAS_FSL_DR_USB 430 #define CONFIG_USB_EHCI 431 432 #ifdef CONFIG_USB_EHCI 433 #define CONFIG_CMD_USB 434 #define CONFIG_USB_STORAGE 435 #define CONFIG_USB_EHCI_FSL 436 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 437 #define CONFIG_CMD_EXT2 438 #endif 439 #endif 440 441 /* 442 * Video 443 */ 444 #define CONFIG_FSL_DCU_FB 445 446 #ifdef CONFIG_FSL_DCU_FB 447 #define CONFIG_VIDEO 448 #define CONFIG_CMD_BMP 449 #define CONFIG_CFB_CONSOLE 450 #define CONFIG_VGA_AS_SINGLE_DEVICE 451 #define CONFIG_VIDEO_LOGO 452 #define CONFIG_VIDEO_BMP_LOGO 453 454 #define CONFIG_FSL_DIU_CH7301 455 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0 456 #define CONFIG_SYS_I2C_QIXIS_ADDR 0x66 457 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 458 #endif 459 460 /* 461 * eTSEC 462 */ 463 #define CONFIG_TSEC_ENET 464 465 #ifdef CONFIG_TSEC_ENET 466 #define CONFIG_MII 467 #define CONFIG_MII_DEFAULT_TSEC 3 468 #define CONFIG_TSEC1 1 469 #define CONFIG_TSEC1_NAME "eTSEC1" 470 #define CONFIG_TSEC2 1 471 #define CONFIG_TSEC2_NAME "eTSEC2" 472 #define CONFIG_TSEC3 1 473 #define CONFIG_TSEC3_NAME "eTSEC3" 474 475 #define TSEC1_PHY_ADDR 1 476 #define TSEC2_PHY_ADDR 2 477 #define TSEC3_PHY_ADDR 3 478 479 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 480 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 481 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 482 483 #define TSEC1_PHYIDX 0 484 #define TSEC2_PHYIDX 0 485 #define TSEC3_PHYIDX 0 486 487 #define CONFIG_ETHPRIME "eTSEC1" 488 489 #define CONFIG_PHY_GIGE 490 #define CONFIG_PHYLIB 491 #define CONFIG_PHY_REALTEK 492 493 #define CONFIG_HAS_ETH0 494 #define CONFIG_HAS_ETH1 495 #define CONFIG_HAS_ETH2 496 497 #define CONFIG_FSL_SGMII_RISER 1 498 #define SGMII_RISER_PHY_OFFSET 0x1b 499 500 #ifdef CONFIG_FSL_SGMII_RISER 501 #define CONFIG_SYS_TBIPA_VALUE 8 502 #endif 503 504 #endif 505 506 /* PCIe */ 507 #define CONFIG_PCI /* Enable PCI/PCIE */ 508 #define CONFIG_PCIE1 /* PCIE controler 1 */ 509 #define CONFIG_PCIE2 /* PCIE controler 2 */ 510 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 511 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" 512 513 #define CONFIG_CMD_PING 514 #define CONFIG_CMD_DHCP 515 #define CONFIG_CMD_MII 516 #define CONFIG_CMD_NET 517 518 #define CONFIG_CMDLINE_TAG 519 #define CONFIG_CMDLINE_EDITING 520 521 #ifdef CONFIG_QSPI_BOOT 522 #undef CONFIG_CMD_IMLS 523 #else 524 #define CONFIG_CMD_IMLS 525 #endif 526 527 #define CONFIG_ARMV7_NONSEC 528 #define CONFIG_ARMV7_VIRT 529 #define CONFIG_PEN_ADDR_BIG_ENDIAN 530 #define CONFIG_LS102XA_NS_ACCESS 531 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 532 #define CONFIG_TIMER_CLK_FREQ 12500000 533 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 534 535 #define CONFIG_HWCONFIG 536 #define HWCONFIG_BUFFER_SIZE 128 537 538 #define CONFIG_BOOTDELAY 3 539 540 #define CONFIG_SYS_QE_FW_ADDR 0x67f40000 541 542 #ifdef CONFIG_LPUART 543 #define CONFIG_EXTRA_ENV_SETTINGS \ 544 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ 545 "fdt_high=0xcfffffff\0" \ 546 "initrd_high=0xcfffffff\0" \ 547 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 548 #else 549 #define CONFIG_EXTRA_ENV_SETTINGS \ 550 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 551 "fdt_high=0xcfffffff\0" \ 552 "initrd_high=0xcfffffff\0" \ 553 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 554 #endif 555 556 /* 557 * Miscellaneous configurable options 558 */ 559 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 560 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 561 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 562 #define CONFIG_AUTO_COMPLETE 563 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 564 #define CONFIG_SYS_PBSIZE \ 565 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 566 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 567 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 568 569 #define CONFIG_CMD_ENV_EXISTS 570 #define CONFIG_CMD_GREPENV 571 #define CONFIG_CMD_MEMINFO 572 #define CONFIG_CMD_MEMTEST 573 #define CONFIG_SYS_MEMTEST_START 0x80000000 574 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 575 576 #define CONFIG_SYS_LOAD_ADDR 0x82000000 577 578 #define CONFIG_LS102XA_STREAM_ID 579 580 /* 581 * Stack sizes 582 * The stack sizes are set up in start.S using the settings below 583 */ 584 #define CONFIG_STACKSIZE (30 * 1024) 585 586 #define CONFIG_SYS_INIT_SP_OFFSET \ 587 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 588 #define CONFIG_SYS_INIT_SP_ADDR \ 589 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 590 591 #ifdef CONFIG_SPL_BUILD 592 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 593 #else 594 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 595 #endif 596 597 /* 598 * Environment 599 */ 600 #define CONFIG_ENV_OVERWRITE 601 602 #if defined(CONFIG_SD_BOOT) 603 #define CONFIG_ENV_OFFSET 0x100000 604 #define CONFIG_ENV_IS_IN_MMC 605 #define CONFIG_SYS_MMC_ENV_DEV 0 606 #define CONFIG_ENV_SIZE 0x2000 607 #elif defined(CONFIG_QSPI_BOOT) 608 #define CONFIG_ENV_IS_IN_SPI_FLASH 609 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 610 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 611 #define CONFIG_ENV_SECT_SIZE 0x10000 612 #elif defined(CONFIG_NAND_BOOT) 613 #define CONFIG_ENV_IS_IN_NAND 614 #define CONFIG_ENV_SIZE 0x2000 615 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 616 #else 617 #define CONFIG_ENV_IS_IN_FLASH 618 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 619 #define CONFIG_ENV_SIZE 0x2000 620 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 621 #endif 622 623 #define CONFIG_OF_LIBFDT 624 #define CONFIG_OF_BOARD_SETUP 625 #define CONFIG_CMD_BOOTZ 626 627 #define CONFIG_MISC_INIT_R 628 629 /* Hash command with SHA acceleration supported in hardware */ 630 #define CONFIG_CMD_HASH 631 #define CONFIG_SHA_HW_ACCEL 632 633 #ifdef CONFIG_SECURE_BOOT 634 #define CONFIG_CMD_BLOB 635 #endif 636 637 #endif 638