1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2014 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __CONFIG_H 7 #define __CONFIG_H 8 9 #define CONFIG_ARMV7_PSCI_1_0 10 11 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 12 13 #define CONFIG_SYS_FSL_CLK 14 15 #define CONFIG_SKIP_LOWLEVEL_INIT 16 17 #define CONFIG_DEEP_SLEEP 18 19 /* 20 * Size of malloc() pool 21 */ 22 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 23 24 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 25 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 26 27 #ifndef __ASSEMBLY__ 28 unsigned long get_board_sys_clk(void); 29 unsigned long get_board_ddr_clk(void); 30 #endif 31 32 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 33 #define CONFIG_SYS_CLK_FREQ 100000000 34 #define CONFIG_DDR_CLK_FREQ 100000000 35 #define CONFIG_QIXIS_I2C_ACCESS 36 #else 37 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 38 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 39 #endif 40 41 #ifdef CONFIG_RAMBOOT_PBL 42 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg 43 #endif 44 45 #ifdef CONFIG_SD_BOOT 46 #ifdef CONFIG_SD_BOOT_QSPI 47 #define CONFIG_SYS_FSL_PBL_RCW \ 48 board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg 49 #else 50 #define CONFIG_SYS_FSL_PBL_RCW \ 51 board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg 52 #endif 53 54 #define CONFIG_SPL_TEXT_BASE 0x10000000 55 #define CONFIG_SPL_MAX_SIZE 0x1a000 56 #define CONFIG_SPL_STACK 0x1001d000 57 #define CONFIG_SPL_PAD_TO 0x1c000 58 59 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 60 CONFIG_SYS_MONITOR_LEN) 61 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 62 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 63 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 64 #define CONFIG_SYS_MONITOR_LEN 0xc0000 65 #endif 66 67 #ifdef CONFIG_NAND_BOOT 68 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg 69 70 #define CONFIG_SPL_TEXT_BASE 0x10000000 71 #define CONFIG_SPL_MAX_SIZE 0x1a000 72 #define CONFIG_SPL_STACK 0x1001d000 73 #define CONFIG_SPL_PAD_TO 0x1c000 74 75 #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10) 76 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 77 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 78 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 79 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 80 81 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 82 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 83 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 84 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 85 #define CONFIG_SYS_MONITOR_LEN 0x80000 86 #endif 87 88 #define CONFIG_NR_DRAM_BANKS 1 89 90 #define CONFIG_DDR_SPD 91 #define SPD_EEPROM_ADDRESS 0x51 92 #define CONFIG_SYS_SPD_BUS_NUM 0 93 94 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 95 #ifndef CONFIG_SYS_FSL_DDR4 96 #define CONFIG_SYS_DDR_RAW_TIMING 97 #endif 98 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 99 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 100 101 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 102 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 103 104 #define CONFIG_DDR_ECC 105 #ifdef CONFIG_DDR_ECC 106 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 107 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 108 #endif 109 110 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ 111 !defined(CONFIG_QSPI_BOOT) 112 #define CONFIG_U_QE 113 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 114 #endif 115 116 /* 117 * IFC Definitions 118 */ 119 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 120 #define CONFIG_FSL_IFC 121 #define CONFIG_SYS_FLASH_BASE 0x60000000 122 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 123 124 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 125 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 126 CSPR_PORT_SIZE_16 | \ 127 CSPR_MSEL_NOR | \ 128 CSPR_V) 129 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 130 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 131 + 0x8000000) | \ 132 CSPR_PORT_SIZE_16 | \ 133 CSPR_MSEL_NOR | \ 134 CSPR_V) 135 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 136 137 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 138 CSOR_NOR_TRHZ_80) 139 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 140 FTIM0_NOR_TEADC(0x5) | \ 141 FTIM0_NOR_TEAHC(0x5)) 142 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 143 FTIM1_NOR_TRAD_NOR(0x1a) | \ 144 FTIM1_NOR_TSEQRAD_NOR(0x13)) 145 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 146 FTIM2_NOR_TCH(0x4) | \ 147 FTIM2_NOR_TWPH(0xe) | \ 148 FTIM2_NOR_TWP(0x1c)) 149 #define CONFIG_SYS_NOR_FTIM3 0 150 151 #define CONFIG_FLASH_CFI_DRIVER 152 #define CONFIG_SYS_FLASH_CFI 153 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 154 #define CONFIG_SYS_FLASH_QUIET_TEST 155 #define CONFIG_FLASH_SHOW_PROGRESS 45 156 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 157 #define CONFIG_SYS_WRITE_SWAPPED_DATA 158 159 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 160 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 161 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 162 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 163 164 #define CONFIG_SYS_FLASH_EMPTY_INFO 165 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 166 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 167 168 /* 169 * NAND Flash Definitions 170 */ 171 #define CONFIG_NAND_FSL_IFC 172 173 #define CONFIG_SYS_NAND_BASE 0x7e800000 174 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 175 176 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 177 178 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 179 | CSPR_PORT_SIZE_8 \ 180 | CSPR_MSEL_NAND \ 181 | CSPR_V) 182 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 183 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 184 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 185 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 186 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 187 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 188 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 189 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 190 191 #define CONFIG_SYS_NAND_ONFI_DETECTION 192 193 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 194 FTIM0_NAND_TWP(0x18) | \ 195 FTIM0_NAND_TWCHT(0x7) | \ 196 FTIM0_NAND_TWH(0xa)) 197 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 198 FTIM1_NAND_TWBE(0x39) | \ 199 FTIM1_NAND_TRR(0xe) | \ 200 FTIM1_NAND_TRP(0x18)) 201 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 202 FTIM2_NAND_TREH(0xa) | \ 203 FTIM2_NAND_TWHRE(0x1e)) 204 #define CONFIG_SYS_NAND_FTIM3 0x0 205 206 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 207 #define CONFIG_SYS_MAX_NAND_DEVICE 1 208 209 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 210 #endif 211 212 /* 213 * QIXIS Definitions 214 */ 215 #define CONFIG_FSL_QIXIS 216 217 #ifdef CONFIG_FSL_QIXIS 218 #define QIXIS_BASE 0x7fb00000 219 #define QIXIS_BASE_PHYS QIXIS_BASE 220 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 221 #define QIXIS_LBMAP_SWITCH 6 222 #define QIXIS_LBMAP_MASK 0x0f 223 #define QIXIS_LBMAP_SHIFT 0 224 #define QIXIS_LBMAP_DFLTBANK 0x00 225 #define QIXIS_LBMAP_ALTBANK 0x04 226 #define QIXIS_PWR_CTL 0x21 227 #define QIXIS_PWR_CTL_POWEROFF 0x80 228 #define QIXIS_RST_CTL_RESET 0x44 229 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 230 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 231 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 232 #define QIXIS_CTL_SYS 0x5 233 #define QIXIS_CTL_SYS_EVTSW_MASK 0x0c 234 #define QIXIS_CTL_SYS_EVTSW_IRQ 0x04 235 #define QIXIS_RST_FORCE_3 0x45 236 #define QIXIS_RST_FORCE_3_PCIESLOT1 0x80 237 #define QIXIS_PWR_CTL2 0x21 238 #define QIXIS_PWR_CTL2_PCTL 0x2 239 240 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 241 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 242 CSPR_PORT_SIZE_8 | \ 243 CSPR_MSEL_GPCM | \ 244 CSPR_V) 245 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 246 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 247 CSOR_NOR_NOR_MODE_AVD_NOR | \ 248 CSOR_NOR_TRHZ_80) 249 250 /* 251 * QIXIS Timing parameters for IFC GPCM 252 */ 253 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \ 254 FTIM0_GPCM_TEADC(0xe) | \ 255 FTIM0_GPCM_TEAHC(0xe)) 256 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \ 257 FTIM1_GPCM_TRAD(0x1f)) 258 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \ 259 FTIM2_GPCM_TCH(0xe) | \ 260 FTIM2_GPCM_TWP(0xf0)) 261 #define CONFIG_SYS_FPGA_FTIM3 0x0 262 #endif 263 264 #if defined(CONFIG_NAND_BOOT) 265 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 266 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 267 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 268 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 269 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 270 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 271 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 272 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 273 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 274 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 275 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 276 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 277 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 278 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 279 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 280 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 281 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 282 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 283 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 284 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 285 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 286 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 287 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 288 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 289 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 290 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 291 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 292 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 293 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 294 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 295 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 296 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 297 #else 298 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 299 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 300 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 301 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 302 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 303 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 304 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 305 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 306 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 307 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 308 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 309 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 310 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 311 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 312 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 313 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 314 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 315 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 316 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 317 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 318 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 319 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 320 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 321 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 322 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 323 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 324 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 325 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 326 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 327 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 328 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 329 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 330 #endif 331 332 /* 333 * Serial Port 334 */ 335 #ifdef CONFIG_LPUART 336 #define CONFIG_LPUART_32B_REG 337 #else 338 #define CONFIG_SYS_NS16550_SERIAL 339 #ifndef CONFIG_DM_SERIAL 340 #define CONFIG_SYS_NS16550_REG_SIZE 1 341 #endif 342 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 343 #endif 344 345 /* 346 * I2C 347 */ 348 #define CONFIG_SYS_I2C 349 #define CONFIG_SYS_I2C_MXC 350 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 351 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 352 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 353 354 /* EEPROM */ 355 #define CONFIG_ID_EEPROM 356 #define CONFIG_SYS_I2C_EEPROM_NXID 357 #define CONFIG_SYS_EEPROM_BUS_NUM 0 358 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 359 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 360 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 361 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 362 363 /* 364 * I2C bus multiplexer 365 */ 366 #define I2C_MUX_PCA_ADDR_PRI 0x77 367 #define I2C_MUX_CH_DEFAULT 0x8 368 #define I2C_MUX_CH_CH7301 0xC 369 370 /* 371 * MMC 372 */ 373 374 /* SPI */ 375 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 376 /* QSPI */ 377 #define QSPI0_AMBA_BASE 0x40000000 378 #define FSL_QSPI_FLASH_SIZE (1 << 24) 379 #define FSL_QSPI_FLASH_NUM 2 380 381 /* DSPI */ 382 383 /* DM SPI */ 384 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 385 #define CONFIG_DM_SPI_FLASH 386 #define CONFIG_SPI_FLASH_DATAFLASH 387 #endif 388 #endif 389 390 /* 391 * Video 392 */ 393 #ifdef CONFIG_VIDEO_FSL_DCU_FB 394 #define CONFIG_VIDEO_LOGO 395 #define CONFIG_VIDEO_BMP_LOGO 396 397 #define CONFIG_FSL_DIU_CH7301 398 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0 399 #define CONFIG_SYS_I2C_QIXIS_ADDR 0x66 400 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 401 #endif 402 403 /* 404 * eTSEC 405 */ 406 407 #ifdef CONFIG_TSEC_ENET 408 #define CONFIG_MII 409 #define CONFIG_MII_DEFAULT_TSEC 3 410 #define CONFIG_TSEC1 1 411 #define CONFIG_TSEC1_NAME "eTSEC1" 412 #define CONFIG_TSEC2 1 413 #define CONFIG_TSEC2_NAME "eTSEC2" 414 #define CONFIG_TSEC3 1 415 #define CONFIG_TSEC3_NAME "eTSEC3" 416 417 #define TSEC1_PHY_ADDR 1 418 #define TSEC2_PHY_ADDR 2 419 #define TSEC3_PHY_ADDR 3 420 421 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 422 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 423 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 424 425 #define TSEC1_PHYIDX 0 426 #define TSEC2_PHYIDX 0 427 #define TSEC3_PHYIDX 0 428 429 #define CONFIG_ETHPRIME "eTSEC1" 430 431 #define CONFIG_PHY_REALTEK 432 433 #define CONFIG_HAS_ETH0 434 #define CONFIG_HAS_ETH1 435 #define CONFIG_HAS_ETH2 436 437 #define CONFIG_FSL_SGMII_RISER 1 438 #define SGMII_RISER_PHY_OFFSET 0x1b 439 440 #ifdef CONFIG_FSL_SGMII_RISER 441 #define CONFIG_SYS_TBIPA_VALUE 8 442 #endif 443 444 #endif 445 446 /* PCIe */ 447 #define CONFIG_PCIE1 /* PCIE controller 1 */ 448 #define CONFIG_PCIE2 /* PCIE controller 2 */ 449 450 #ifdef CONFIG_PCI 451 #define CONFIG_PCI_SCAN_SHOW 452 #endif 453 454 #define CONFIG_CMDLINE_TAG 455 456 #define CONFIG_PEN_ADDR_BIG_ENDIAN 457 #define CONFIG_LAYERSCAPE_NS_ACCESS 458 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 459 #define COUNTER_FREQUENCY 12500000 460 461 #define CONFIG_HWCONFIG 462 #define HWCONFIG_BUFFER_SIZE 256 463 464 #define CONFIG_FSL_DEVICE_DISABLE 465 466 467 #define CONFIG_SYS_QE_FW_ADDR 0x60940000 468 469 #ifdef CONFIG_LPUART 470 #define CONFIG_EXTRA_ENV_SETTINGS \ 471 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ 472 "fdt_high=0xffffffff\0" \ 473 "initrd_high=0xffffffff\0" \ 474 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 475 #else 476 #define CONFIG_EXTRA_ENV_SETTINGS \ 477 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 478 "fdt_high=0xffffffff\0" \ 479 "initrd_high=0xffffffff\0" \ 480 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 481 #endif 482 483 /* 484 * Miscellaneous configurable options 485 */ 486 487 #define CONFIG_SYS_MEMTEST_START 0x80000000 488 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 489 490 #define CONFIG_SYS_LOAD_ADDR 0x82000000 491 492 #define CONFIG_LS102XA_STREAM_ID 493 494 #define CONFIG_SYS_INIT_SP_OFFSET \ 495 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 496 #define CONFIG_SYS_INIT_SP_ADDR \ 497 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 498 499 #ifdef CONFIG_SPL_BUILD 500 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 501 #else 502 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 503 #endif 504 505 /* 506 * Environment 507 */ 508 #define CONFIG_ENV_OVERWRITE 509 510 #if defined(CONFIG_SD_BOOT) 511 #define CONFIG_ENV_OFFSET 0x300000 512 #define CONFIG_SYS_MMC_ENV_DEV 0 513 #define CONFIG_ENV_SIZE 0x2000 514 #elif defined(CONFIG_QSPI_BOOT) 515 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 516 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ 517 #define CONFIG_ENV_SECT_SIZE 0x10000 518 #elif defined(CONFIG_NAND_BOOT) 519 #define CONFIG_ENV_SIZE 0x2000 520 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 521 #else 522 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) 523 #define CONFIG_ENV_SIZE 0x2000 524 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 525 #endif 526 527 #define CONFIG_MISC_INIT_R 528 529 #include <asm/fsl_secure_boot.h> 530 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 531 532 #endif 533