1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #include <config_cmd_default.h> 11 12 #define CONFIG_LS102XA 13 14 #define CONFIG_SYS_GENERIC_BOARD 15 16 #define CONFIG_DISPLAY_CPUINFO 17 #define CONFIG_DISPLAY_BOARDINFO 18 19 #define CONFIG_SKIP_LOWLEVEL_INIT 20 #define CONFIG_BOARD_EARLY_INIT_F 21 22 /* 23 * Size of malloc() pool 24 */ 25 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 26 27 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 28 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 29 30 /* 31 * Generic Timer Definitions 32 */ 33 #define GENERIC_TIMER_CLK 12500000 34 35 #ifndef __ASSEMBLY__ 36 unsigned long get_board_sys_clk(void); 37 unsigned long get_board_ddr_clk(void); 38 #endif 39 40 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 41 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 42 43 #ifndef CONFIG_SYS_TEXT_BASE 44 #define CONFIG_SYS_TEXT_BASE 0x67f80000 45 #endif 46 47 #define CONFIG_NR_DRAM_BANKS 1 48 49 #define CONFIG_DDR_SPD 50 #define SPD_EEPROM_ADDRESS 0x51 51 #define CONFIG_SYS_SPD_BUS_NUM 0 52 53 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 54 #ifndef CONFIG_SYS_FSL_DDR4 55 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ 56 #define CONFIG_SYS_DDR_RAW_TIMING 57 #endif 58 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 59 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 60 61 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 62 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 63 64 #define CONFIG_DDR_ECC 65 #ifdef CONFIG_DDR_ECC 66 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 67 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 68 #endif 69 70 #define CONFIG_SYS_HAS_SERDES 71 72 #define CONFIG_FSL_CAAM /* Enable CAAM */ 73 /* 74 * IFC Definitions 75 */ 76 #define CONFIG_FSL_IFC 77 #define CONFIG_SYS_FLASH_BASE 0x60000000 78 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 79 80 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 81 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 82 CSPR_PORT_SIZE_16 | \ 83 CSPR_MSEL_NOR | \ 84 CSPR_V) 85 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 86 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 87 + 0x8000000) | \ 88 CSPR_PORT_SIZE_16 | \ 89 CSPR_MSEL_NOR | \ 90 CSPR_V) 91 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 92 93 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 94 CSOR_NOR_TRHZ_80) 95 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 96 FTIM0_NOR_TEADC(0x5) | \ 97 FTIM0_NOR_TEAHC(0x5)) 98 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 99 FTIM1_NOR_TRAD_NOR(0x1a) | \ 100 FTIM1_NOR_TSEQRAD_NOR(0x13)) 101 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 102 FTIM2_NOR_TCH(0x4) | \ 103 FTIM2_NOR_TWPH(0xe) | \ 104 FTIM2_NOR_TWP(0x1c)) 105 #define CONFIG_SYS_NOR_FTIM3 0 106 107 #define CONFIG_FLASH_CFI_DRIVER 108 #define CONFIG_SYS_FLASH_CFI 109 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 110 #define CONFIG_SYS_FLASH_QUIET_TEST 111 #define CONFIG_FLASH_SHOW_PROGRESS 45 112 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 113 114 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 115 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 116 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 117 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 118 119 #define CONFIG_SYS_FLASH_EMPTY_INFO 120 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 121 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 122 123 /* 124 * NAND Flash Definitions 125 */ 126 #define CONFIG_NAND_FSL_IFC 127 128 #define CONFIG_SYS_NAND_BASE 0x7e800000 129 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 130 131 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 132 133 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 134 | CSPR_PORT_SIZE_8 \ 135 | CSPR_MSEL_NAND \ 136 | CSPR_V) 137 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 138 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 139 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 140 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 141 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 142 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 143 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 144 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 145 146 #define CONFIG_SYS_NAND_ONFI_DETECTION 147 148 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 149 FTIM0_NAND_TWP(0x18) | \ 150 FTIM0_NAND_TWCHT(0x7) | \ 151 FTIM0_NAND_TWH(0xa)) 152 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 153 FTIM1_NAND_TWBE(0x39) | \ 154 FTIM1_NAND_TRR(0xe) | \ 155 FTIM1_NAND_TRP(0x18)) 156 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 157 FTIM2_NAND_TREH(0xa) | \ 158 FTIM2_NAND_TWHRE(0x1e)) 159 #define CONFIG_SYS_NAND_FTIM3 0x0 160 161 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 162 #define CONFIG_SYS_MAX_NAND_DEVICE 1 163 #define CONFIG_MTD_NAND_VERIFY_WRITE 164 #define CONFIG_CMD_NAND 165 166 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 167 168 /* 169 * QIXIS Definitions 170 */ 171 #define CONFIG_FSL_QIXIS 172 173 #ifdef CONFIG_FSL_QIXIS 174 #define QIXIS_BASE 0x7fb00000 175 #define QIXIS_BASE_PHYS QIXIS_BASE 176 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 177 #define QIXIS_LBMAP_SWITCH 6 178 #define QIXIS_LBMAP_MASK 0x0f 179 #define QIXIS_LBMAP_SHIFT 0 180 #define QIXIS_LBMAP_DFLTBANK 0x00 181 #define QIXIS_LBMAP_ALTBANK 0x04 182 #define QIXIS_RST_CTL_RESET 0x44 183 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 184 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 185 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 186 187 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 188 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 189 CSPR_PORT_SIZE_8 | \ 190 CSPR_MSEL_GPCM | \ 191 CSPR_V) 192 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 193 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 194 CSOR_NOR_NOR_MODE_AVD_NOR | \ 195 CSOR_NOR_TRHZ_80) 196 197 /* 198 * QIXIS Timing parameters for IFC GPCM 199 */ 200 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \ 201 FTIM0_GPCM_TEADC(0xe) | \ 202 FTIM0_GPCM_TEAHC(0xe)) 203 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \ 204 FTIM1_GPCM_TRAD(0x1f)) 205 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \ 206 FTIM2_GPCM_TCH(0xe) | \ 207 FTIM2_GPCM_TWP(0xf0)) 208 #define CONFIG_SYS_FPGA_FTIM3 0x0 209 #endif 210 211 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 212 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 213 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 214 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 215 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 216 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 217 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 218 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 219 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 220 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 221 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 222 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 223 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 224 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 225 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 226 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 227 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 228 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 229 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 230 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 231 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 232 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 233 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 234 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 235 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 236 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 237 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 238 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 239 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 240 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 241 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 242 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 243 244 /* 245 * Serial Port 246 */ 247 #define CONFIG_CONS_INDEX 1 248 #define CONFIG_SYS_NS16550 249 #define CONFIG_SYS_NS16550_SERIAL 250 #define CONFIG_SYS_NS16550_REG_SIZE 1 251 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 252 253 #define CONFIG_BAUDRATE 115200 254 255 /* 256 * I2C 257 */ 258 #define CONFIG_CMD_I2C 259 #define CONFIG_SYS_I2C 260 #define CONFIG_SYS_I2C_MXC 261 262 /* 263 * I2C bus multiplexer 264 */ 265 #define I2C_MUX_PCA_ADDR_PRI 0x77 266 #define I2C_MUX_CH_DEFAULT 0x8 267 268 /* 269 * MMC 270 */ 271 #define CONFIG_MMC 272 #define CONFIG_CMD_MMC 273 #define CONFIG_FSL_ESDHC 274 #define CONFIG_GENERIC_MMC 275 276 /* 277 * eTSEC 278 */ 279 #define CONFIG_TSEC_ENET 280 281 #ifdef CONFIG_TSEC_ENET 282 #define CONFIG_MII 283 #define CONFIG_MII_DEFAULT_TSEC 3 284 #define CONFIG_TSEC1 1 285 #define CONFIG_TSEC1_NAME "eTSEC1" 286 #define CONFIG_TSEC2 1 287 #define CONFIG_TSEC2_NAME "eTSEC2" 288 #define CONFIG_TSEC3 1 289 #define CONFIG_TSEC3_NAME "eTSEC3" 290 291 #define TSEC1_PHY_ADDR 1 292 #define TSEC2_PHY_ADDR 2 293 #define TSEC3_PHY_ADDR 3 294 295 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 296 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 297 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 298 299 #define TSEC1_PHYIDX 0 300 #define TSEC2_PHYIDX 0 301 #define TSEC3_PHYIDX 0 302 303 #define CONFIG_ETHPRIME "eTSEC1" 304 305 #define CONFIG_PHY_GIGE 306 #define CONFIG_PHYLIB 307 #define CONFIG_PHY_REALTEK 308 309 #define CONFIG_HAS_ETH0 310 #define CONFIG_HAS_ETH1 311 #define CONFIG_HAS_ETH2 312 313 #define CONFIG_FSL_SGMII_RISER 1 314 #define SGMII_RISER_PHY_OFFSET 0x1b 315 316 #ifdef CONFIG_FSL_SGMII_RISER 317 #define CONFIG_SYS_TBIPA_VALUE 8 318 #endif 319 320 #endif 321 #define CONFIG_CMD_PING 322 #define CONFIG_CMD_DHCP 323 #define CONFIG_CMD_MII 324 #define CONFIG_CMD_NET 325 326 #define CONFIG_CMDLINE_TAG 327 #define CONFIG_CMDLINE_EDITING 328 #define CONFIG_CMD_IMLS 329 330 #define CONFIG_HWCONFIG 331 #define HWCONFIG_BUFFER_SIZE 128 332 333 #define CONFIG_BOOTDELAY 3 334 335 #define CONFIG_EXTRA_ENV_SETTINGS \ 336 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 337 "fdt_high=0xcfffffff\0" \ 338 "initrd_high=0xcfffffff\0" \ 339 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 340 341 /* 342 * Miscellaneous configurable options 343 */ 344 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 345 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 346 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 347 #define CONFIG_SYS_PROMPT "=> " 348 #define CONFIG_AUTO_COMPLETE 349 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 350 #define CONFIG_SYS_PBSIZE \ 351 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 352 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 353 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 354 355 #define CONFIG_CMD_ENV_EXISTS 356 #define CONFIG_CMD_GREPENV 357 #define CONFIG_CMD_MEMINFO 358 #define CONFIG_CMD_MEMTEST 359 #define CONFIG_SYS_MEMTEST_START 0x80000000 360 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 361 362 #define CONFIG_SYS_LOAD_ADDR 0x82000000 363 #define CONFIG_SYS_HZ 1000 364 365 /* 366 * Stack sizes 367 * The stack sizes are set up in start.S using the settings below 368 */ 369 #define CONFIG_STACKSIZE (30 * 1024) 370 371 #define CONFIG_SYS_INIT_SP_OFFSET \ 372 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 373 #define CONFIG_SYS_INIT_SP_ADDR \ 374 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 375 376 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 377 378 /* 379 * Environment 380 */ 381 #define CONFIG_ENV_OVERWRITE 382 383 #define CONFIG_ENV_IS_IN_FLASH 384 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 385 #define CONFIG_ENV_SIZE 0x2000 386 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 387 388 #define CONFIG_OF_LIBFDT 389 #define CONFIG_OF_BOARD_SETUP 390 #define CONFIG_CMD_BOOTZ 391 392 #define CONFIG_MISC_INIT_R 393 394 /* Hash command with SHA acceleration supported in hardware */ 395 #define CONFIG_CMD_HASH 396 #define CONFIG_SHA_HW_ACCEL 397 398 #ifdef CONFIG_SECURE_BOOT 399 #define CONFIG_CMD_BLOB 400 #endif 401 402 #endif 403