1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_LS102XA 11 12 #define CONFIG_ARMV7_PSCI_1_0 13 14 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 15 16 #define CONFIG_SYS_FSL_CLK 17 18 #define CONFIG_SKIP_LOWLEVEL_INIT 19 20 #define CONFIG_DEEP_SLEEP 21 22 /* 23 * Size of malloc() pool 24 */ 25 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 26 27 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 28 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 29 30 #ifndef __ASSEMBLY__ 31 unsigned long get_board_sys_clk(void); 32 unsigned long get_board_ddr_clk(void); 33 #endif 34 35 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 36 #define CONFIG_SYS_CLK_FREQ 100000000 37 #define CONFIG_DDR_CLK_FREQ 100000000 38 #define CONFIG_QIXIS_I2C_ACCESS 39 #else 40 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 41 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 42 #endif 43 44 #ifdef CONFIG_RAMBOOT_PBL 45 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg 46 #endif 47 48 #ifdef CONFIG_SD_BOOT 49 #ifdef CONFIG_SD_BOOT_QSPI 50 #define CONFIG_SYS_FSL_PBL_RCW \ 51 board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg 52 #else 53 #define CONFIG_SYS_FSL_PBL_RCW \ 54 board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg 55 #endif 56 #define CONFIG_SPL_FRAMEWORK 57 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 58 59 #define CONFIG_SPL_TEXT_BASE 0x10000000 60 #define CONFIG_SPL_MAX_SIZE 0x1a000 61 #define CONFIG_SPL_STACK 0x1001d000 62 #define CONFIG_SPL_PAD_TO 0x1c000 63 #define CONFIG_SYS_TEXT_BASE 0x82000000 64 65 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 66 CONFIG_SYS_MONITOR_LEN) 67 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 68 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 69 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 70 #define CONFIG_SYS_MONITOR_LEN 0xc0000 71 #endif 72 73 #ifdef CONFIG_QSPI_BOOT 74 #define CONFIG_SYS_TEXT_BASE 0x40010000 75 #endif 76 77 #ifdef CONFIG_NAND_BOOT 78 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg 79 #define CONFIG_SPL_FRAMEWORK 80 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 81 82 #define CONFIG_SPL_TEXT_BASE 0x10000000 83 #define CONFIG_SPL_MAX_SIZE 0x1a000 84 #define CONFIG_SPL_STACK 0x1001d000 85 #define CONFIG_SPL_PAD_TO 0x1c000 86 #define CONFIG_SYS_TEXT_BASE 0x82000000 87 88 #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10) 89 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO 90 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 91 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 92 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 93 94 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 95 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 96 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 97 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 98 #define CONFIG_SYS_MONITOR_LEN 0x80000 99 #endif 100 101 #ifndef CONFIG_SYS_TEXT_BASE 102 #define CONFIG_SYS_TEXT_BASE 0x60100000 103 #endif 104 105 #define CONFIG_NR_DRAM_BANKS 1 106 107 #define CONFIG_DDR_SPD 108 #define SPD_EEPROM_ADDRESS 0x51 109 #define CONFIG_SYS_SPD_BUS_NUM 0 110 111 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 112 #ifndef CONFIG_SYS_FSL_DDR4 113 #define CONFIG_SYS_DDR_RAW_TIMING 114 #endif 115 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 116 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 117 118 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 119 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 120 121 #define CONFIG_DDR_ECC 122 #ifdef CONFIG_DDR_ECC 123 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 124 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 125 #endif 126 127 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ 128 !defined(CONFIG_QSPI_BOOT) 129 #define CONFIG_U_QE 130 #endif 131 132 /* 133 * IFC Definitions 134 */ 135 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) 136 #define CONFIG_FSL_IFC 137 #define CONFIG_SYS_FLASH_BASE 0x60000000 138 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 139 140 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) 141 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 142 CSPR_PORT_SIZE_16 | \ 143 CSPR_MSEL_NOR | \ 144 CSPR_V) 145 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0) 146 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 147 + 0x8000000) | \ 148 CSPR_PORT_SIZE_16 | \ 149 CSPR_MSEL_NOR | \ 150 CSPR_V) 151 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 152 153 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 154 CSOR_NOR_TRHZ_80) 155 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 156 FTIM0_NOR_TEADC(0x5) | \ 157 FTIM0_NOR_TEAHC(0x5)) 158 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 159 FTIM1_NOR_TRAD_NOR(0x1a) | \ 160 FTIM1_NOR_TSEQRAD_NOR(0x13)) 161 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 162 FTIM2_NOR_TCH(0x4) | \ 163 FTIM2_NOR_TWPH(0xe) | \ 164 FTIM2_NOR_TWP(0x1c)) 165 #define CONFIG_SYS_NOR_FTIM3 0 166 167 #define CONFIG_FLASH_CFI_DRIVER 168 #define CONFIG_SYS_FLASH_CFI 169 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 170 #define CONFIG_SYS_FLASH_QUIET_TEST 171 #define CONFIG_FLASH_SHOW_PROGRESS 45 172 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 173 #define CONFIG_SYS_WRITE_SWAPPED_DATA 174 175 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 176 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 177 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 178 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 179 180 #define CONFIG_SYS_FLASH_EMPTY_INFO 181 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ 182 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} 183 184 /* 185 * NAND Flash Definitions 186 */ 187 #define CONFIG_NAND_FSL_IFC 188 189 #define CONFIG_SYS_NAND_BASE 0x7e800000 190 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 191 192 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 193 194 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 195 | CSPR_PORT_SIZE_8 \ 196 | CSPR_MSEL_NAND \ 197 | CSPR_V) 198 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 199 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 200 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 201 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 202 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 203 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 204 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 205 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 206 207 #define CONFIG_SYS_NAND_ONFI_DETECTION 208 209 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 210 FTIM0_NAND_TWP(0x18) | \ 211 FTIM0_NAND_TWCHT(0x7) | \ 212 FTIM0_NAND_TWH(0xa)) 213 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 214 FTIM1_NAND_TWBE(0x39) | \ 215 FTIM1_NAND_TRR(0xe) | \ 216 FTIM1_NAND_TRP(0x18)) 217 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 218 FTIM2_NAND_TREH(0xa) | \ 219 FTIM2_NAND_TWHRE(0x1e)) 220 #define CONFIG_SYS_NAND_FTIM3 0x0 221 222 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 223 #define CONFIG_SYS_MAX_NAND_DEVICE 1 224 #define CONFIG_CMD_NAND 225 226 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 227 #endif 228 229 /* 230 * QIXIS Definitions 231 */ 232 #define CONFIG_FSL_QIXIS 233 234 #ifdef CONFIG_FSL_QIXIS 235 #define QIXIS_BASE 0x7fb00000 236 #define QIXIS_BASE_PHYS QIXIS_BASE 237 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 238 #define QIXIS_LBMAP_SWITCH 6 239 #define QIXIS_LBMAP_MASK 0x0f 240 #define QIXIS_LBMAP_SHIFT 0 241 #define QIXIS_LBMAP_DFLTBANK 0x00 242 #define QIXIS_LBMAP_ALTBANK 0x04 243 #define QIXIS_PWR_CTL 0x21 244 #define QIXIS_PWR_CTL_POWEROFF 0x80 245 #define QIXIS_RST_CTL_RESET 0x44 246 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 247 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 248 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 249 #define QIXIS_CTL_SYS 0x5 250 #define QIXIS_CTL_SYS_EVTSW_MASK 0x0c 251 #define QIXIS_CTL_SYS_EVTSW_IRQ 0x04 252 #define QIXIS_RST_FORCE_3 0x45 253 #define QIXIS_RST_FORCE_3_PCIESLOT1 0x80 254 #define QIXIS_PWR_CTL2 0x21 255 #define QIXIS_PWR_CTL2_PCTL 0x2 256 257 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) 258 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ 259 CSPR_PORT_SIZE_8 | \ 260 CSPR_MSEL_GPCM | \ 261 CSPR_V) 262 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) 263 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ 264 CSOR_NOR_NOR_MODE_AVD_NOR | \ 265 CSOR_NOR_TRHZ_80) 266 267 /* 268 * QIXIS Timing parameters for IFC GPCM 269 */ 270 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \ 271 FTIM0_GPCM_TEADC(0xe) | \ 272 FTIM0_GPCM_TEAHC(0xe)) 273 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \ 274 FTIM1_GPCM_TRAD(0x1f)) 275 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \ 276 FTIM2_GPCM_TCH(0xe) | \ 277 FTIM2_GPCM_TWP(0xf0)) 278 #define CONFIG_SYS_FPGA_FTIM3 0x0 279 #endif 280 281 #if defined(CONFIG_NAND_BOOT) 282 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 283 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 284 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 285 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 286 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 287 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 288 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 289 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 290 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 291 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 292 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 293 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 294 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 295 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 296 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 297 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 298 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 299 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 300 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 301 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 302 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 303 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 304 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 305 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 306 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 307 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 308 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 309 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 310 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 311 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 312 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 313 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 314 #else 315 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 316 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 317 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 318 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 319 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 320 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 321 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 322 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 323 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 324 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 325 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 326 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 327 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 328 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 329 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 330 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 331 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 332 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 333 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 334 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 335 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 336 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 337 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 338 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 339 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT 340 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR 341 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK 342 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR 343 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 344 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 345 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 346 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 347 #endif 348 349 /* 350 * Serial Port 351 */ 352 #ifdef CONFIG_LPUART 353 #define CONFIG_LPUART_32B_REG 354 #else 355 #define CONFIG_CONS_INDEX 1 356 #define CONFIG_SYS_NS16550_SERIAL 357 #ifndef CONFIG_DM_SERIAL 358 #define CONFIG_SYS_NS16550_REG_SIZE 1 359 #endif 360 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 361 #endif 362 363 /* 364 * I2C 365 */ 366 #define CONFIG_SYS_I2C 367 #define CONFIG_SYS_I2C_MXC 368 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 369 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 370 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 371 372 /* 373 * I2C bus multiplexer 374 */ 375 #define I2C_MUX_PCA_ADDR_PRI 0x77 376 #define I2C_MUX_CH_DEFAULT 0x8 377 #define I2C_MUX_CH_CH7301 0xC 378 379 /* 380 * MMC 381 */ 382 #define CONFIG_FSL_ESDHC 383 384 /* SPI */ 385 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 386 /* QSPI */ 387 #define QSPI0_AMBA_BASE 0x40000000 388 #define FSL_QSPI_FLASH_SIZE (1 << 24) 389 #define FSL_QSPI_FLASH_NUM 2 390 391 /* DSPI */ 392 393 /* DM SPI */ 394 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 395 #define CONFIG_DM_SPI_FLASH 396 #define CONFIG_SPI_FLASH_DATAFLASH 397 #endif 398 #endif 399 400 /* 401 * USB 402 */ 403 /* EHCI Support - disbaled by default */ 404 /*#define CONFIG_HAS_FSL_DR_USB*/ 405 406 #ifdef CONFIG_HAS_FSL_DR_USB 407 #define CONFIG_USB_EHCI 408 #define CONFIG_USB_EHCI_FSL 409 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 410 #endif 411 412 /*XHCI Support - enabled by default*/ 413 #define CONFIG_HAS_FSL_XHCI_USB 414 415 #ifdef CONFIG_HAS_FSL_XHCI_USB 416 #define CONFIG_USB_XHCI_FSL 417 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 418 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 419 #endif 420 421 /* 422 * Video 423 */ 424 #ifdef CONFIG_VIDEO_FSL_DCU_FB 425 #define CONFIG_CMD_BMP 426 #define CONFIG_VIDEO_LOGO 427 #define CONFIG_VIDEO_BMP_LOGO 428 429 #define CONFIG_FSL_DIU_CH7301 430 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0 431 #define CONFIG_SYS_I2C_QIXIS_ADDR 0x66 432 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 433 #endif 434 435 /* 436 * eTSEC 437 */ 438 #define CONFIG_TSEC_ENET 439 440 #ifdef CONFIG_TSEC_ENET 441 #define CONFIG_MII 442 #define CONFIG_MII_DEFAULT_TSEC 3 443 #define CONFIG_TSEC1 1 444 #define CONFIG_TSEC1_NAME "eTSEC1" 445 #define CONFIG_TSEC2 1 446 #define CONFIG_TSEC2_NAME "eTSEC2" 447 #define CONFIG_TSEC3 1 448 #define CONFIG_TSEC3_NAME "eTSEC3" 449 450 #define TSEC1_PHY_ADDR 1 451 #define TSEC2_PHY_ADDR 2 452 #define TSEC3_PHY_ADDR 3 453 454 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 455 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 456 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 457 458 #define TSEC1_PHYIDX 0 459 #define TSEC2_PHYIDX 0 460 #define TSEC3_PHYIDX 0 461 462 #define CONFIG_ETHPRIME "eTSEC1" 463 464 #define CONFIG_PHY_GIGE 465 #define CONFIG_PHYLIB 466 #define CONFIG_PHY_REALTEK 467 468 #define CONFIG_HAS_ETH0 469 #define CONFIG_HAS_ETH1 470 #define CONFIG_HAS_ETH2 471 472 #define CONFIG_FSL_SGMII_RISER 1 473 #define SGMII_RISER_PHY_OFFSET 0x1b 474 475 #ifdef CONFIG_FSL_SGMII_RISER 476 #define CONFIG_SYS_TBIPA_VALUE 8 477 #endif 478 479 #endif 480 481 /* PCIe */ 482 #define CONFIG_PCIE1 /* PCIE controller 1 */ 483 #define CONFIG_PCIE2 /* PCIE controller 2 */ 484 485 #ifdef CONFIG_PCI 486 #define CONFIG_PCI_SCAN_SHOW 487 #define CONFIG_CMD_PCI 488 #endif 489 490 #define CONFIG_CMDLINE_TAG 491 #define CONFIG_CMDLINE_EDITING 492 493 #define CONFIG_PEN_ADDR_BIG_ENDIAN 494 #define CONFIG_LAYERSCAPE_NS_ACCESS 495 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 496 #define COUNTER_FREQUENCY 12500000 497 498 #define CONFIG_HWCONFIG 499 #define HWCONFIG_BUFFER_SIZE 256 500 501 #define CONFIG_FSL_DEVICE_DISABLE 502 503 504 #define CONFIG_SYS_QE_FW_ADDR 0x600c0000 505 506 #ifdef CONFIG_LPUART 507 #define CONFIG_EXTRA_ENV_SETTINGS \ 508 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ 509 "fdt_high=0xffffffff\0" \ 510 "initrd_high=0xffffffff\0" \ 511 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 512 #else 513 #define CONFIG_EXTRA_ENV_SETTINGS \ 514 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 515 "fdt_high=0xffffffff\0" \ 516 "initrd_high=0xffffffff\0" \ 517 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" 518 #endif 519 520 /* 521 * Miscellaneous configurable options 522 */ 523 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 524 #define CONFIG_AUTO_COMPLETE 525 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 526 #define CONFIG_SYS_PBSIZE \ 527 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 528 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 529 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 530 531 #define CONFIG_SYS_MEMTEST_START 0x80000000 532 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 533 534 #define CONFIG_SYS_LOAD_ADDR 0x82000000 535 536 #define CONFIG_LS102XA_STREAM_ID 537 538 #define CONFIG_SYS_INIT_SP_OFFSET \ 539 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 540 #define CONFIG_SYS_INIT_SP_ADDR \ 541 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 542 543 #ifdef CONFIG_SPL_BUILD 544 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 545 #else 546 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 547 #endif 548 549 /* 550 * Environment 551 */ 552 #define CONFIG_ENV_OVERWRITE 553 554 #if defined(CONFIG_SD_BOOT) 555 #define CONFIG_ENV_OFFSET 0x100000 556 #define CONFIG_ENV_IS_IN_MMC 557 #define CONFIG_SYS_MMC_ENV_DEV 0 558 #define CONFIG_ENV_SIZE 0x2000 559 #elif defined(CONFIG_QSPI_BOOT) 560 #define CONFIG_ENV_IS_IN_SPI_FLASH 561 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 562 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 563 #define CONFIG_ENV_SECT_SIZE 0x10000 564 #elif defined(CONFIG_NAND_BOOT) 565 #define CONFIG_ENV_IS_IN_NAND 566 #define CONFIG_ENV_SIZE 0x2000 567 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 568 #else 569 #define CONFIG_ENV_IS_IN_FLASH 570 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 571 #define CONFIG_ENV_SIZE 0x2000 572 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 573 #endif 574 575 #define CONFIG_MISC_INIT_R 576 577 /* Hash command with SHA acceleration supported in hardware */ 578 #ifdef CONFIG_FSL_CAAM 579 #define CONFIG_CMD_HASH 580 #define CONFIG_SHA_HW_ACCEL 581 #endif 582 583 #include <asm/fsl_secure_boot.h> 584 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 585 586 #endif 587