1 /* 2 * Copyright 2016 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 11 12 #define CONFIG_SYS_FSL_CLK 13 14 /* 15 * Size of malloc() pool 16 */ 17 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 18 19 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 20 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 21 22 /* XHCI Support - enabled by default */ 23 #define CONFIG_HAS_FSL_XHCI_USB 24 25 #ifdef CONFIG_HAS_FSL_XHCI_USB 26 #define CONFIG_USB_XHCI_FSL 27 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 28 #endif 29 30 #define CONFIG_SYS_CLK_FREQ 100000000 31 #define CONFIG_DDR_CLK_FREQ 100000000 32 33 /* 34 * DDR: 800 MHz ( 1600 MT/s data rate ) 35 */ 36 37 #define DDR_SDRAM_CFG 0x470c0008 38 #define DDR_CS0_BNDS 0x008000bf 39 #define DDR_CS0_CONFIG 0x80014302 40 #define DDR_TIMING_CFG_0 0x50550004 41 #define DDR_TIMING_CFG_1 0xbcb38c56 42 #define DDR_TIMING_CFG_2 0x0040d120 43 #define DDR_TIMING_CFG_3 0x010e1000 44 #define DDR_TIMING_CFG_4 0x00000001 45 #define DDR_TIMING_CFG_5 0x03401400 46 #define DDR_SDRAM_CFG_2 0x00401010 47 #define DDR_SDRAM_MODE 0x00061c60 48 #define DDR_SDRAM_MODE_2 0x00180000 49 #define DDR_SDRAM_INTERVAL 0x18600618 50 #define DDR_DDR_WRLVL_CNTL 0x8655f605 51 #define DDR_DDR_WRLVL_CNTL_2 0x05060607 52 #define DDR_DDR_WRLVL_CNTL_3 0x05050505 53 #define DDR_DDR_CDR1 0x80040000 54 #define DDR_DDR_CDR2 0x00000001 55 #define DDR_SDRAM_CLK_CNTL 0x02000000 56 #define DDR_DDR_ZQ_CNTL 0x89080600 57 #define DDR_CS0_CONFIG_2 0 58 #define DDR_SDRAM_CFG_MEM_EN 0x80000000 59 #define SDRAM_CFG2_D_INIT 0x00000010 60 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080 61 #define SDRAM_CFG2_FRC_SR 0x80000000 62 #define SDRAM_CFG_BI 0x00000001 63 64 #ifdef CONFIG_RAMBOOT_PBL 65 #define CONFIG_SYS_FSL_PBL_PBI \ 66 board/freescale/ls1021aiot/ls102xa_pbi.cfg 67 #endif 68 69 #ifdef CONFIG_SD_BOOT 70 #define CONFIG_SYS_FSL_PBL_RCW \ 71 board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg 72 #define CONFIG_SPL_FRAMEWORK 73 #define CONFIG_SPL_LIBCOMMON_SUPPORT 74 #define CONFIG_SPL_LIBGENERIC_SUPPORT 75 #define CONFIG_SPL_ENV_SUPPORT 76 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 77 #define CONFIG_SPL_I2C_SUPPORT 78 #define CONFIG_SPL_WATCHDOG_SUPPORT 79 #define CONFIG_SPL_SERIAL_SUPPORT 80 #define CONFIG_SPL_MMC_SUPPORT 81 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 82 83 #define CONFIG_SPL_TEXT_BASE 0x10000000 84 #define CONFIG_SPL_MAX_SIZE 0x1a000 85 #define CONFIG_SPL_STACK 0x1001d000 86 #define CONFIG_SPL_PAD_TO 0x1c000 87 #define CONFIG_SYS_TEXT_BASE 0x82000000 88 89 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 90 CONFIG_SYS_MONITOR_LEN) 91 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 92 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 93 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 94 #define CONFIG_SYS_MONITOR_LEN 0x80000 95 #endif 96 97 #ifdef CONFIG_QSPI_BOOT 98 #define CONFIG_SYS_TEXT_BASE 0x40010000 99 #endif 100 101 #define CONFIG_NR_DRAM_BANKS 1 102 103 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 104 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 105 106 /* 107 * Serial Port 108 */ 109 #define CONFIG_CONS_INDEX 1 110 #define CONFIG_SYS_NS16550_SERIAL 111 #define CONFIG_SYS_NS16550_REG_SIZE 1 112 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 113 114 /* 115 * I2C 116 */ 117 #define CONFIG_CMD_I2C 118 #define CONFIG_SYS_I2C 119 #define CONFIG_SYS_I2C_MXC 120 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 121 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 122 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 123 124 /* EEPROM */ 125 #define CONFIG_ID_EEPROM 126 #define CONFIG_SYS_I2C_EEPROM_NXID 127 #define CONFIG_SYS_EEPROM_BUS_NUM 0 128 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 129 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 130 131 /* 132 * MMC 133 */ 134 #define CONFIG_CMD_MMC 135 #define CONFIG_FSL_ESDHC 136 137 /* SATA */ 138 #define CONFIG_LIBATA 139 #define CONFIG_SCSI_AHCI 140 #define CONFIG_SCSI_AHCI_PLAT 141 #ifndef PCI_DEVICE_ID_FREESCALE_AHCI 142 #define PCI_DEVICE_ID_FREESCALE_AHCI 0x0440 143 #endif 144 #define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_FREESCALE, \ 145 PCI_DEVICE_ID_FREESCALE_AHCI} 146 147 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 148 #define CONFIG_SYS_SCSI_MAX_LUN 1 149 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 150 CONFIG_SYS_SCSI_MAX_LUN) 151 152 /* SPI */ 153 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 154 #define CONFIG_SPI_FLASH_SPANSION 155 156 /* QSPI */ 157 #define QSPI0_AMBA_BASE 0x40000000 158 #define FSL_QSPI_FLASH_SIZE (1 << 24) 159 #define FSL_QSPI_FLASH_NUM 2 160 #define CONFIG_SPI_FLASH_BAR 161 #define CONFIG_SPI_FLASH_SPANSION 162 #endif 163 164 /* DM SPI */ 165 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 166 #define CONFIG_CMD_SF 167 #define CONFIG_DM_SPI_FLASH 168 #endif 169 170 /* 171 * eTSEC 172 */ 173 #define CONFIG_TSEC_ENET 174 175 #ifdef CONFIG_TSEC_ENET 176 #define CONFIG_MII 177 #define CONFIG_MII_DEFAULT_TSEC 1 178 #define CONFIG_TSEC1 1 179 #define CONFIG_TSEC1_NAME "eTSEC1" 180 #define CONFIG_TSEC2 1 181 #define CONFIG_TSEC2_NAME "eTSEC2" 182 183 #define TSEC1_PHY_ADDR 1 184 #define TSEC2_PHY_ADDR 3 185 186 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 187 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 188 189 #define TSEC1_PHYIDX 0 190 #define TSEC2_PHYIDX 0 191 192 #define CONFIG_ETHPRIME "eTSEC2" 193 194 #define CONFIG_PHY_ATHEROS 195 196 #define CONFIG_HAS_ETH0 197 #define CONFIG_HAS_ETH1 198 #define CONFIG_HAS_ETH2 199 #endif 200 201 /* PCIe */ 202 #define CONFIG_PCIE1 /* PCIE controler 1 */ 203 #define CONFIG_PCIE2 /* PCIE controler 2 */ 204 205 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" 206 207 #ifdef CONFIG_PCI 208 #define CONFIG_PCI_SCAN_SHOW 209 #endif 210 211 #define CONFIG_CMD_PING 212 #define CONFIG_CMD_DHCP 213 #define CONFIG_CMD_MII 214 215 #define CONFIG_CMDLINE_TAG 216 #define CONFIG_CMDLINE_EDITING 217 218 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT) 219 #undef CONFIG_CMD_IMLS 220 #endif 221 222 #define CONFIG_PEN_ADDR_BIG_ENDIAN 223 #define CONFIG_LAYERSCAPE_NS_ACCESS 224 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 225 #define COUNTER_FREQUENCY 12500000 226 227 #define CONFIG_HWCONFIG 228 #define HWCONFIG_BUFFER_SIZE 256 229 230 #define CONFIG_FSL_DEVICE_DISABLE 231 232 #define CONFIG_EXTRA_ENV_SETTINGS \ 233 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 234 "initrd_high=0xffffffff\0" \ 235 "fdt_high=0xffffffff\0" 236 237 /* 238 * Miscellaneous configurable options 239 */ 240 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 241 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 242 #define CONFIG_AUTO_COMPLETE 243 244 #define CONFIG_CMD_GREPENV 245 #define CONFIG_CMD_MEMINFO 246 247 #define CONFIG_SYS_LOAD_ADDR 0x82000000 248 249 #define CONFIG_LS102XA_STREAM_ID 250 251 #define CONFIG_SYS_INIT_SP_OFFSET \ 252 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 253 #define CONFIG_SYS_INIT_SP_ADDR \ 254 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 255 256 #ifdef CONFIG_SPL_BUILD 257 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 258 #else 259 /* start of monitor */ 260 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 261 #endif 262 263 #define CONFIG_SYS_QE_FW_ADDR 0x67f40000 264 265 /* 266 * Environment 267 */ 268 269 #define CONFIG_ENV_OVERWRITE 270 271 #if defined(CONFIG_SD_BOOT) 272 #define CONFIG_ENV_OFFSET 0x100000 273 #define CONFIG_SYS_MMC_ENV_DEV 0 274 #define CONFIG_ENV_SIZE 0x2000 275 #elif defined(CONFIG_QSPI_BOOT) 276 #define CONFIG_ENV_SIZE 0x2000 277 #define CONFIG_ENV_OFFSET 0x100000 278 #define CONFIG_ENV_SECT_SIZE 0x10000 279 #endif 280 281 #define CONFIG_OF_BOARD_SETUP 282 #define CONFIG_OF_STDOUT_VIA_ALIAS 283 #define CONFIG_CMD_BOOTZ 284 285 #define CONFIG_MISC_INIT_R 286 287 #include <asm/fsl_secure_boot.h> 288 289 #endif 290