1 /* 2 * Copyright 2016 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 11 12 #define CONFIG_SYS_FSL_CLK 13 14 /* 15 * Size of malloc() pool 16 */ 17 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 18 19 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 20 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 21 22 #define CONFIG_SYS_CLK_FREQ 100000000 23 #define CONFIG_DDR_CLK_FREQ 100000000 24 25 /* 26 * DDR: 800 MHz ( 1600 MT/s data rate ) 27 */ 28 29 #define DDR_SDRAM_CFG 0x470c0008 30 #define DDR_CS0_BNDS 0x008000bf 31 #define DDR_CS0_CONFIG 0x80014302 32 #define DDR_TIMING_CFG_0 0x50550004 33 #define DDR_TIMING_CFG_1 0xbcb38c56 34 #define DDR_TIMING_CFG_2 0x0040d120 35 #define DDR_TIMING_CFG_3 0x010e1000 36 #define DDR_TIMING_CFG_4 0x00000001 37 #define DDR_TIMING_CFG_5 0x03401400 38 #define DDR_SDRAM_CFG_2 0x00401010 39 #define DDR_SDRAM_MODE 0x00061c60 40 #define DDR_SDRAM_MODE_2 0x00180000 41 #define DDR_SDRAM_INTERVAL 0x18600618 42 #define DDR_DDR_WRLVL_CNTL 0x8655f605 43 #define DDR_DDR_WRLVL_CNTL_2 0x05060607 44 #define DDR_DDR_WRLVL_CNTL_3 0x05050505 45 #define DDR_DDR_CDR1 0x80040000 46 #define DDR_DDR_CDR2 0x00000001 47 #define DDR_SDRAM_CLK_CNTL 0x02000000 48 #define DDR_DDR_ZQ_CNTL 0x89080600 49 #define DDR_CS0_CONFIG_2 0 50 #define DDR_SDRAM_CFG_MEM_EN 0x80000000 51 #define SDRAM_CFG2_D_INIT 0x00000010 52 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080 53 #define SDRAM_CFG2_FRC_SR 0x80000000 54 #define SDRAM_CFG_BI 0x00000001 55 56 #ifdef CONFIG_RAMBOOT_PBL 57 #define CONFIG_SYS_FSL_PBL_PBI \ 58 board/freescale/ls1021aiot/ls102xa_pbi.cfg 59 #endif 60 61 #ifdef CONFIG_SD_BOOT 62 #define CONFIG_SYS_FSL_PBL_RCW \ 63 board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg 64 #define CONFIG_SPL_LIBCOMMON_SUPPORT 65 #define CONFIG_SPL_LIBGENERIC_SUPPORT 66 #define CONFIG_SPL_ENV_SUPPORT 67 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 68 #define CONFIG_SPL_I2C_SUPPORT 69 #define CONFIG_SPL_WATCHDOG_SUPPORT 70 #define CONFIG_SPL_SERIAL_SUPPORT 71 #define CONFIG_SPL_MMC_SUPPORT 72 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 73 74 #define CONFIG_SPL_TEXT_BASE 0x10000000 75 #define CONFIG_SPL_MAX_SIZE 0x1a000 76 #define CONFIG_SPL_STACK 0x1001d000 77 #define CONFIG_SPL_PAD_TO 0x1c000 78 79 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 80 CONFIG_SYS_MONITOR_LEN) 81 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 82 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 83 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 84 #define CONFIG_SYS_MONITOR_LEN 0x80000 85 #endif 86 87 #define CONFIG_NR_DRAM_BANKS 1 88 89 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 90 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 91 92 /* 93 * Serial Port 94 */ 95 #define CONFIG_SYS_NS16550_SERIAL 96 #define CONFIG_SYS_NS16550_REG_SIZE 1 97 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 98 99 /* 100 * I2C 101 */ 102 #define CONFIG_CMD_I2C 103 #define CONFIG_SYS_I2C 104 #define CONFIG_SYS_I2C_MXC 105 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 106 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 107 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 108 109 /* EEPROM */ 110 #define CONFIG_ID_EEPROM 111 #define CONFIG_SYS_I2C_EEPROM_NXID 112 #define CONFIG_SYS_EEPROM_BUS_NUM 0 113 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 114 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 115 116 /* 117 * MMC 118 */ 119 #define CONFIG_CMD_MMC 120 #define CONFIG_FSL_ESDHC 121 122 /* SATA */ 123 #define CONFIG_SCSI_AHCI_PLAT 124 #ifndef PCI_DEVICE_ID_FREESCALE_AHCI 125 #define PCI_DEVICE_ID_FREESCALE_AHCI 0x0440 126 #endif 127 #define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_FREESCALE, \ 128 PCI_DEVICE_ID_FREESCALE_AHCI} 129 130 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 131 #define CONFIG_SYS_SCSI_MAX_LUN 1 132 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 133 CONFIG_SYS_SCSI_MAX_LUN) 134 135 /* SPI */ 136 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 137 #define CONFIG_SPI_FLASH_SPANSION 138 139 /* QSPI */ 140 #define QSPI0_AMBA_BASE 0x40000000 141 #define FSL_QSPI_FLASH_SIZE (1 << 24) 142 #define FSL_QSPI_FLASH_NUM 2 143 #define CONFIG_SPI_FLASH_BAR 144 #define CONFIG_SPI_FLASH_SPANSION 145 #endif 146 147 /* DM SPI */ 148 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 149 #define CONFIG_CMD_SF 150 #define CONFIG_DM_SPI_FLASH 151 #endif 152 153 /* 154 * eTSEC 155 */ 156 #define CONFIG_TSEC_ENET 157 158 #ifdef CONFIG_TSEC_ENET 159 #define CONFIG_MII 160 #define CONFIG_MII_DEFAULT_TSEC 1 161 #define CONFIG_TSEC1 1 162 #define CONFIG_TSEC1_NAME "eTSEC1" 163 #define CONFIG_TSEC2 1 164 #define CONFIG_TSEC2_NAME "eTSEC2" 165 166 #define TSEC1_PHY_ADDR 1 167 #define TSEC2_PHY_ADDR 3 168 169 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 170 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 171 172 #define TSEC1_PHYIDX 0 173 #define TSEC2_PHYIDX 0 174 175 #define CONFIG_ETHPRIME "eTSEC2" 176 177 #define CONFIG_PHY_ATHEROS 178 179 #define CONFIG_HAS_ETH0 180 #define CONFIG_HAS_ETH1 181 #define CONFIG_HAS_ETH2 182 #endif 183 184 /* PCIe */ 185 #define CONFIG_PCIE1 /* PCIE controler 1 */ 186 #define CONFIG_PCIE2 /* PCIE controler 2 */ 187 188 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" 189 190 #ifdef CONFIG_PCI 191 #define CONFIG_PCI_SCAN_SHOW 192 #endif 193 194 #define CONFIG_CMD_MII 195 196 #define CONFIG_CMDLINE_TAG 197 198 #define CONFIG_PEN_ADDR_BIG_ENDIAN 199 #define CONFIG_LAYERSCAPE_NS_ACCESS 200 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 201 #define COUNTER_FREQUENCY 12500000 202 203 #define CONFIG_HWCONFIG 204 #define HWCONFIG_BUFFER_SIZE 256 205 206 #define CONFIG_FSL_DEVICE_DISABLE 207 208 #define CONFIG_EXTRA_ENV_SETTINGS \ 209 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 210 "initrd_high=0xffffffff\0" \ 211 "fdt_high=0xffffffff\0" 212 213 /* 214 * Miscellaneous configurable options 215 */ 216 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 217 218 #define CONFIG_CMD_GREPENV 219 #define CONFIG_CMD_MEMINFO 220 221 #define CONFIG_SYS_LOAD_ADDR 0x82000000 222 223 #define CONFIG_LS102XA_STREAM_ID 224 225 #define CONFIG_SYS_INIT_SP_OFFSET \ 226 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 227 #define CONFIG_SYS_INIT_SP_ADDR \ 228 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 229 230 #ifdef CONFIG_SPL_BUILD 231 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 232 #else 233 /* start of monitor */ 234 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 235 #endif 236 237 #define CONFIG_SYS_QE_FW_ADDR 0x67f40000 238 239 /* 240 * Environment 241 */ 242 243 #define CONFIG_ENV_OVERWRITE 244 245 #if defined(CONFIG_SD_BOOT) 246 #define CONFIG_ENV_OFFSET 0x100000 247 #define CONFIG_SYS_MMC_ENV_DEV 0 248 #define CONFIG_ENV_SIZE 0x2000 249 #elif defined(CONFIG_QSPI_BOOT) 250 #define CONFIG_ENV_SIZE 0x2000 251 #define CONFIG_ENV_OFFSET 0x100000 252 #define CONFIG_ENV_SECT_SIZE 0x10000 253 #endif 254 255 #define CONFIG_OF_BOARD_SETUP 256 #define CONFIG_OF_STDOUT_VIA_ALIAS 257 258 #define CONFIG_MISC_INIT_R 259 260 #include <asm/fsl_secure_boot.h> 261 262 #endif 263