1 /* 2 * Copyright 2016 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 11 12 #define CONFIG_SYS_FSL_CLK 13 14 /* 15 * Size of malloc() pool 16 */ 17 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 18 19 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 20 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 21 22 #define CONFIG_SYS_CLK_FREQ 100000000 23 #define CONFIG_DDR_CLK_FREQ 100000000 24 25 /* 26 * DDR: 800 MHz ( 1600 MT/s data rate ) 27 */ 28 29 #define DDR_SDRAM_CFG 0x470c0008 30 #define DDR_CS0_BNDS 0x008000bf 31 #define DDR_CS0_CONFIG 0x80014302 32 #define DDR_TIMING_CFG_0 0x50550004 33 #define DDR_TIMING_CFG_1 0xbcb38c56 34 #define DDR_TIMING_CFG_2 0x0040d120 35 #define DDR_TIMING_CFG_3 0x010e1000 36 #define DDR_TIMING_CFG_4 0x00000001 37 #define DDR_TIMING_CFG_5 0x03401400 38 #define DDR_SDRAM_CFG_2 0x00401010 39 #define DDR_SDRAM_MODE 0x00061c60 40 #define DDR_SDRAM_MODE_2 0x00180000 41 #define DDR_SDRAM_INTERVAL 0x18600618 42 #define DDR_DDR_WRLVL_CNTL 0x8655f605 43 #define DDR_DDR_WRLVL_CNTL_2 0x05060607 44 #define DDR_DDR_WRLVL_CNTL_3 0x05050505 45 #define DDR_DDR_CDR1 0x80040000 46 #define DDR_DDR_CDR2 0x00000001 47 #define DDR_SDRAM_CLK_CNTL 0x02000000 48 #define DDR_DDR_ZQ_CNTL 0x89080600 49 #define DDR_CS0_CONFIG_2 0 50 #define DDR_SDRAM_CFG_MEM_EN 0x80000000 51 #define SDRAM_CFG2_D_INIT 0x00000010 52 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080 53 #define SDRAM_CFG2_FRC_SR 0x80000000 54 #define SDRAM_CFG_BI 0x00000001 55 56 #ifdef CONFIG_RAMBOOT_PBL 57 #define CONFIG_SYS_FSL_PBL_PBI \ 58 board/freescale/ls1021aiot/ls102xa_pbi.cfg 59 #endif 60 61 #ifdef CONFIG_SD_BOOT 62 #define CONFIG_SYS_FSL_PBL_RCW \ 63 board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg 64 #define CONFIG_SPL_FRAMEWORK 65 #define CONFIG_SPL_LIBCOMMON_SUPPORT 66 #define CONFIG_SPL_LIBGENERIC_SUPPORT 67 #define CONFIG_SPL_ENV_SUPPORT 68 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 69 #define CONFIG_SPL_I2C_SUPPORT 70 #define CONFIG_SPL_WATCHDOG_SUPPORT 71 #define CONFIG_SPL_SERIAL_SUPPORT 72 #define CONFIG_SPL_MMC_SUPPORT 73 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 74 75 #define CONFIG_SPL_TEXT_BASE 0x10000000 76 #define CONFIG_SPL_MAX_SIZE 0x1a000 77 #define CONFIG_SPL_STACK 0x1001d000 78 #define CONFIG_SPL_PAD_TO 0x1c000 79 #define CONFIG_SYS_TEXT_BASE 0x82000000 80 81 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 82 CONFIG_SYS_MONITOR_LEN) 83 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 84 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 85 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 86 #define CONFIG_SYS_MONITOR_LEN 0x80000 87 #endif 88 89 #ifdef CONFIG_QSPI_BOOT 90 #define CONFIG_SYS_TEXT_BASE 0x40010000 91 #endif 92 93 #define CONFIG_NR_DRAM_BANKS 1 94 95 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 96 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 97 98 /* 99 * Serial Port 100 */ 101 #define CONFIG_CONS_INDEX 1 102 #define CONFIG_SYS_NS16550_SERIAL 103 #define CONFIG_SYS_NS16550_REG_SIZE 1 104 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 105 106 /* 107 * I2C 108 */ 109 #define CONFIG_CMD_I2C 110 #define CONFIG_SYS_I2C 111 #define CONFIG_SYS_I2C_MXC 112 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 113 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 114 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 115 116 /* EEPROM */ 117 #define CONFIG_ID_EEPROM 118 #define CONFIG_SYS_I2C_EEPROM_NXID 119 #define CONFIG_SYS_EEPROM_BUS_NUM 0 120 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 121 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 122 123 /* 124 * MMC 125 */ 126 #define CONFIG_CMD_MMC 127 #define CONFIG_FSL_ESDHC 128 129 /* SATA */ 130 #define CONFIG_SCSI_AHCI_PLAT 131 #ifndef PCI_DEVICE_ID_FREESCALE_AHCI 132 #define PCI_DEVICE_ID_FREESCALE_AHCI 0x0440 133 #endif 134 #define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_FREESCALE, \ 135 PCI_DEVICE_ID_FREESCALE_AHCI} 136 137 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 138 #define CONFIG_SYS_SCSI_MAX_LUN 1 139 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 140 CONFIG_SYS_SCSI_MAX_LUN) 141 142 /* SPI */ 143 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 144 #define CONFIG_SPI_FLASH_SPANSION 145 146 /* QSPI */ 147 #define QSPI0_AMBA_BASE 0x40000000 148 #define FSL_QSPI_FLASH_SIZE (1 << 24) 149 #define FSL_QSPI_FLASH_NUM 2 150 #define CONFIG_SPI_FLASH_BAR 151 #define CONFIG_SPI_FLASH_SPANSION 152 #endif 153 154 /* DM SPI */ 155 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 156 #define CONFIG_CMD_SF 157 #define CONFIG_DM_SPI_FLASH 158 #endif 159 160 /* 161 * eTSEC 162 */ 163 #define CONFIG_TSEC_ENET 164 165 #ifdef CONFIG_TSEC_ENET 166 #define CONFIG_MII 167 #define CONFIG_MII_DEFAULT_TSEC 1 168 #define CONFIG_TSEC1 1 169 #define CONFIG_TSEC1_NAME "eTSEC1" 170 #define CONFIG_TSEC2 1 171 #define CONFIG_TSEC2_NAME "eTSEC2" 172 173 #define TSEC1_PHY_ADDR 1 174 #define TSEC2_PHY_ADDR 3 175 176 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 177 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 178 179 #define TSEC1_PHYIDX 0 180 #define TSEC2_PHYIDX 0 181 182 #define CONFIG_ETHPRIME "eTSEC2" 183 184 #define CONFIG_PHY_ATHEROS 185 186 #define CONFIG_HAS_ETH0 187 #define CONFIG_HAS_ETH1 188 #define CONFIG_HAS_ETH2 189 #endif 190 191 /* PCIe */ 192 #define CONFIG_PCIE1 /* PCIE controler 1 */ 193 #define CONFIG_PCIE2 /* PCIE controler 2 */ 194 195 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" 196 197 #ifdef CONFIG_PCI 198 #define CONFIG_PCI_SCAN_SHOW 199 #endif 200 201 #define CONFIG_CMD_PING 202 #define CONFIG_CMD_DHCP 203 #define CONFIG_CMD_MII 204 205 #define CONFIG_CMDLINE_TAG 206 #define CONFIG_CMDLINE_EDITING 207 208 #define CONFIG_PEN_ADDR_BIG_ENDIAN 209 #define CONFIG_LAYERSCAPE_NS_ACCESS 210 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 211 #define COUNTER_FREQUENCY 12500000 212 213 #define CONFIG_HWCONFIG 214 #define HWCONFIG_BUFFER_SIZE 256 215 216 #define CONFIG_FSL_DEVICE_DISABLE 217 218 #define CONFIG_EXTRA_ENV_SETTINGS \ 219 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 220 "initrd_high=0xffffffff\0" \ 221 "fdt_high=0xffffffff\0" 222 223 /* 224 * Miscellaneous configurable options 225 */ 226 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 227 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 228 #define CONFIG_AUTO_COMPLETE 229 230 #define CONFIG_CMD_GREPENV 231 #define CONFIG_CMD_MEMINFO 232 233 #define CONFIG_SYS_LOAD_ADDR 0x82000000 234 235 #define CONFIG_LS102XA_STREAM_ID 236 237 #define CONFIG_SYS_INIT_SP_OFFSET \ 238 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 239 #define CONFIG_SYS_INIT_SP_ADDR \ 240 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 241 242 #ifdef CONFIG_SPL_BUILD 243 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 244 #else 245 /* start of monitor */ 246 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 247 #endif 248 249 #define CONFIG_SYS_QE_FW_ADDR 0x67f40000 250 251 /* 252 * Environment 253 */ 254 255 #define CONFIG_ENV_OVERWRITE 256 257 #if defined(CONFIG_SD_BOOT) 258 #define CONFIG_ENV_OFFSET 0x100000 259 #define CONFIG_SYS_MMC_ENV_DEV 0 260 #define CONFIG_ENV_SIZE 0x2000 261 #elif defined(CONFIG_QSPI_BOOT) 262 #define CONFIG_ENV_SIZE 0x2000 263 #define CONFIG_ENV_OFFSET 0x100000 264 #define CONFIG_ENV_SECT_SIZE 0x10000 265 #endif 266 267 #define CONFIG_OF_BOARD_SETUP 268 #define CONFIG_OF_STDOUT_VIA_ALIAS 269 270 #define CONFIG_MISC_INIT_R 271 272 #include <asm/fsl_secure_boot.h> 273 274 #endif 275