1 /* 2 * Copyright 2016 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_LS102XA 11 12 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 13 14 #define CONFIG_SYS_FSL_CLK 15 16 #define CONFIG_BOARD_EARLY_INIT_F 17 18 /* 19 * Size of malloc() pool 20 */ 21 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 22 23 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 24 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 25 26 /* XHCI Support - enabled by default */ 27 #define CONFIG_HAS_FSL_XHCI_USB 28 29 #ifdef CONFIG_HAS_FSL_XHCI_USB 30 #define CONFIG_USB_XHCI_FSL 31 #define CONFIG_USB_XHCI_DWC3 32 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 33 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 34 #endif 35 36 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB) 37 #define CONFIG_USB_STORAGE 38 #define CONFIG_CMD_EXT2 39 #endif 40 41 /* 42 * Generic Timer Definitions 43 */ 44 #define GENERIC_TIMER_CLK 12500000 45 46 #define CONFIG_SYS_CLK_FREQ 100000000 47 #define CONFIG_DDR_CLK_FREQ 100000000 48 49 /* 50 * DDR: 800 MHz ( 1600 MT/s data rate ) 51 */ 52 53 #define DDR_SDRAM_CFG 0x470c0008 54 #define DDR_CS0_BNDS 0x008000bf 55 #define DDR_CS0_CONFIG 0x80014302 56 #define DDR_TIMING_CFG_0 0x50550004 57 #define DDR_TIMING_CFG_1 0xbcb38c56 58 #define DDR_TIMING_CFG_2 0x0040d120 59 #define DDR_TIMING_CFG_3 0x010e1000 60 #define DDR_TIMING_CFG_4 0x00000001 61 #define DDR_TIMING_CFG_5 0x03401400 62 #define DDR_SDRAM_CFG_2 0x00401010 63 #define DDR_SDRAM_MODE 0x00061c60 64 #define DDR_SDRAM_MODE_2 0x00180000 65 #define DDR_SDRAM_INTERVAL 0x18600618 66 #define DDR_DDR_WRLVL_CNTL 0x8655f605 67 #define DDR_DDR_WRLVL_CNTL_2 0x05060607 68 #define DDR_DDR_WRLVL_CNTL_3 0x05050505 69 #define DDR_DDR_CDR1 0x80040000 70 #define DDR_DDR_CDR2 0x00000001 71 #define DDR_SDRAM_CLK_CNTL 0x02000000 72 #define DDR_DDR_ZQ_CNTL 0x89080600 73 #define DDR_CS0_CONFIG_2 0 74 #define DDR_SDRAM_CFG_MEM_EN 0x80000000 75 #define SDRAM_CFG2_D_INIT 0x00000010 76 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080 77 #define SDRAM_CFG2_FRC_SR 0x80000000 78 #define SDRAM_CFG_BI 0x00000001 79 80 #ifdef CONFIG_RAMBOOT_PBL 81 #define CONFIG_SYS_FSL_PBL_PBI \ 82 board/freescale/ls1021aiot/ls102xa_pbi.cfg 83 #endif 84 85 #ifdef CONFIG_SD_BOOT 86 #define CONFIG_SYS_FSL_PBL_RCW \ 87 board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg 88 #define CONFIG_SPL_FRAMEWORK 89 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 90 #define CONFIG_SPL_LIBCOMMON_SUPPORT 91 #define CONFIG_SPL_LIBGENERIC_SUPPORT 92 #define CONFIG_SPL_ENV_SUPPORT 93 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 94 #define CONFIG_SPL_I2C_SUPPORT 95 #define CONFIG_SPL_WATCHDOG_SUPPORT 96 #define CONFIG_SPL_SERIAL_SUPPORT 97 #define CONFIG_SPL_MMC_SUPPORT 98 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 99 100 #define CONFIG_SPL_TEXT_BASE 0x10000000 101 #define CONFIG_SPL_MAX_SIZE 0x1a000 102 #define CONFIG_SPL_STACK 0x1001d000 103 #define CONFIG_SPL_PAD_TO 0x1c000 104 #define CONFIG_SYS_TEXT_BASE 0x82000000 105 106 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 107 CONFIG_SYS_MONITOR_LEN) 108 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 109 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 110 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 111 #define CONFIG_SYS_MONITOR_LEN 0x80000 112 #define CONFIG_SYS_NO_FLASH 113 #endif 114 115 #ifdef CONFIG_QSPI_BOOT 116 #define CONFIG_SYS_TEXT_BASE 0x40010000 117 #endif 118 119 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 120 #define CONFIG_SYS_NO_FLASH 121 #endif 122 123 #define CONFIG_NR_DRAM_BANKS 1 124 125 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 126 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 127 128 #define CONFIG_FSL_CAAM /* Enable CAAM */ 129 130 /* 131 * Serial Port 132 */ 133 #define CONFIG_CONS_INDEX 1 134 #define CONFIG_SYS_NS16550_SERIAL 135 #define CONFIG_SYS_NS16550_REG_SIZE 1 136 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 137 #define CONFIG_BAUDRATE 115200 138 139 /* 140 * I2C 141 */ 142 #define CONFIG_CMD_I2C 143 #define CONFIG_SYS_I2C 144 #define CONFIG_SYS_I2C_MXC 145 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 146 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 147 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 148 149 /* EEPROM */ 150 #define CONFIG_ID_EEPROM 151 #define CONFIG_SYS_I2C_EEPROM_NXID 152 #define CONFIG_SYS_EEPROM_BUS_NUM 0 153 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 154 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 155 156 /* 157 * MMC 158 */ 159 #define CONFIG_CMD_MMC 160 #define CONFIG_FSL_ESDHC 161 #define CONFIG_GENERIC_MMC 162 163 /* SATA */ 164 #define CONFIG_BOARD_LATE_INIT 165 #define CONFIG_CMD_SCSI 166 #define CONFIG_LIBATA 167 #define CONFIG_SCSI_AHCI 168 #define CONFIG_SCSI_AHCI_PLAT 169 #ifndef PCI_DEVICE_ID_FREESCALE_AHCI 170 #define PCI_DEVICE_ID_FREESCALE_AHCI 0x0440 171 #endif 172 #define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_FREESCALE, \ 173 PCI_DEVICE_ID_FREESCALE_AHCI} 174 175 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 176 #define CONFIG_SYS_SCSI_MAX_LUN 1 177 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 178 CONFIG_SYS_SCSI_MAX_LUN) 179 180 #define CONFIG_CMD_FAT 181 #define CONFIG_DOS_PARTITION 182 #define CONFIG_PARTITION_UUIDS 183 #define CONFIG_EFI_PARTITION 184 #define CONFIG_CMD_GPT 185 186 /* SPI */ 187 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 188 #define CONFIG_SPI_FLASH_SPANSION 189 190 /* QSPI */ 191 #define QSPI0_AMBA_BASE 0x40000000 192 #define FSL_QSPI_FLASH_SIZE (1 << 24) 193 #define FSL_QSPI_FLASH_NUM 2 194 #define CONFIG_SPI_FLASH_BAR 195 #define CONFIG_SPI_FLASH_SPANSION 196 #endif 197 198 /* DM SPI */ 199 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 200 #define CONFIG_CMD_SF 201 #define CONFIG_DM_SPI_FLASH 202 #endif 203 204 /* 205 * eTSEC 206 */ 207 #define CONFIG_TSEC_ENET 208 209 #ifdef CONFIG_TSEC_ENET 210 #define CONFIG_MII 211 #define CONFIG_MII_DEFAULT_TSEC 1 212 #define CONFIG_TSEC1 1 213 #define CONFIG_TSEC1_NAME "eTSEC1" 214 #define CONFIG_TSEC2 1 215 #define CONFIG_TSEC2_NAME "eTSEC2" 216 217 #define TSEC1_PHY_ADDR 1 218 #define TSEC2_PHY_ADDR 3 219 220 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 221 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 222 223 #define TSEC1_PHYIDX 0 224 #define TSEC2_PHYIDX 0 225 226 #define CONFIG_ETHPRIME "eTSEC2" 227 228 #define CONFIG_PHY_GIGE 229 #define CONFIG_PHYLIB 230 #define CONFIG_PHY_ATHEROS 231 232 #define CONFIG_HAS_ETH0 233 #define CONFIG_HAS_ETH1 234 #define CONFIG_HAS_ETH2 235 #endif 236 237 /* PCIe */ 238 #define CONFIG_PCIE1 /* PCIE controler 1 */ 239 #define CONFIG_PCIE2 /* PCIE controler 2 */ 240 241 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" 242 243 #ifdef CONFIG_PCI 244 #define CONFIG_PCI_SCAN_SHOW 245 #define CONFIG_CMD_PCI 246 #endif 247 248 #define CONFIG_CMD_PING 249 #define CONFIG_CMD_DHCP 250 #define CONFIG_CMD_MII 251 252 #define CONFIG_CMDLINE_TAG 253 #define CONFIG_CMDLINE_EDITING 254 255 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT) 256 #undef CONFIG_CMD_IMLS 257 #endif 258 259 #define CONFIG_PEN_ADDR_BIG_ENDIAN 260 #define CONFIG_LAYERSCAPE_NS_ACCESS 261 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 262 #define CONFIG_TIMER_CLK_FREQ 12500000 263 264 #define CONFIG_HWCONFIG 265 #define HWCONFIG_BUFFER_SIZE 256 266 267 #define CONFIG_FSL_DEVICE_DISABLE 268 269 #define CONFIG_EXTRA_ENV_SETTINGS \ 270 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 271 "initrd_high=0xffffffff\0" \ 272 "fdt_high=0xffffffff\0" 273 274 /* 275 * Miscellaneous configurable options 276 */ 277 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 278 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 279 #define CONFIG_AUTO_COMPLETE 280 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 281 #define CONFIG_SYS_PBSIZE \ 282 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 283 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 284 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 285 286 #define CONFIG_CMD_GREPENV 287 #define CONFIG_CMD_MEMINFO 288 289 #define CONFIG_SYS_LOAD_ADDR 0x82000000 290 291 #define CONFIG_LS102XA_STREAM_ID 292 293 /* 294 * Stack sizes 295 * The stack sizes are set up in start.S using the settings below 296 */ 297 #define CONFIG_STACKSIZE (30 * 1024) 298 299 #define CONFIG_SYS_INIT_SP_OFFSET \ 300 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 301 #define CONFIG_SYS_INIT_SP_ADDR \ 302 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 303 304 #ifdef CONFIG_SPL_BUILD 305 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 306 #else 307 /* start of monitor */ 308 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 309 #endif 310 311 #define CONFIG_SYS_QE_FW_ADDR 0x67f40000 312 313 /* 314 * Environment 315 */ 316 317 #define CONFIG_ENV_OVERWRITE 318 319 #if defined(CONFIG_SD_BOOT) 320 #define CONFIG_ENV_OFFSET 0x100000 321 #define CONFIG_ENV_IS_IN_MMC 322 #define CONFIG_SYS_MMC_ENV_DEV 0 323 #define CONFIG_ENV_SIZE 0x2000 324 #elif defined(CONFIG_QSPI_BOOT) 325 #define CONFIG_ENV_IS_IN_SPI_FLASH 326 #define CONFIG_ENV_SIZE 0x2000 327 #define CONFIG_ENV_OFFSET 0x100000 328 #define CONFIG_ENV_SECT_SIZE 0x10000 329 #endif 330 331 #define CONFIG_OF_BOARD_SETUP 332 #define CONFIG_OF_STDOUT_VIA_ALIAS 333 #define CONFIG_CMD_BOOTZ 334 335 #define CONFIG_MISC_INIT_R 336 337 /* Hash command with SHA acceleration supported in hardware */ 338 339 #ifdef CONFIG_FSL_CAAM 340 341 #define CONFIG_CMD_HASH 342 343 #define CONFIG_SHA_HW_ACCEL 344 345 #endif 346 347 #include <asm/fsl_secure_boot.h> 348 349 #endif 350