1 /* 2 * Copyright 2016 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_LS102XA 11 12 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR 13 14 #define CONFIG_SYS_FSL_CLK 15 16 /* 17 * Size of malloc() pool 18 */ 19 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) 20 21 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR 22 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE 23 24 /* XHCI Support - enabled by default */ 25 #define CONFIG_HAS_FSL_XHCI_USB 26 27 #ifdef CONFIG_HAS_FSL_XHCI_USB 28 #define CONFIG_USB_XHCI_FSL 29 #define CONFIG_USB_XHCI_DWC3 30 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 31 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 32 #endif 33 34 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB) 35 #define CONFIG_USB_STORAGE 36 #define CONFIG_CMD_EXT2 37 #endif 38 39 #define CONFIG_SYS_CLK_FREQ 100000000 40 #define CONFIG_DDR_CLK_FREQ 100000000 41 42 /* 43 * DDR: 800 MHz ( 1600 MT/s data rate ) 44 */ 45 46 #define DDR_SDRAM_CFG 0x470c0008 47 #define DDR_CS0_BNDS 0x008000bf 48 #define DDR_CS0_CONFIG 0x80014302 49 #define DDR_TIMING_CFG_0 0x50550004 50 #define DDR_TIMING_CFG_1 0xbcb38c56 51 #define DDR_TIMING_CFG_2 0x0040d120 52 #define DDR_TIMING_CFG_3 0x010e1000 53 #define DDR_TIMING_CFG_4 0x00000001 54 #define DDR_TIMING_CFG_5 0x03401400 55 #define DDR_SDRAM_CFG_2 0x00401010 56 #define DDR_SDRAM_MODE 0x00061c60 57 #define DDR_SDRAM_MODE_2 0x00180000 58 #define DDR_SDRAM_INTERVAL 0x18600618 59 #define DDR_DDR_WRLVL_CNTL 0x8655f605 60 #define DDR_DDR_WRLVL_CNTL_2 0x05060607 61 #define DDR_DDR_WRLVL_CNTL_3 0x05050505 62 #define DDR_DDR_CDR1 0x80040000 63 #define DDR_DDR_CDR2 0x00000001 64 #define DDR_SDRAM_CLK_CNTL 0x02000000 65 #define DDR_DDR_ZQ_CNTL 0x89080600 66 #define DDR_CS0_CONFIG_2 0 67 #define DDR_SDRAM_CFG_MEM_EN 0x80000000 68 #define SDRAM_CFG2_D_INIT 0x00000010 69 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080 70 #define SDRAM_CFG2_FRC_SR 0x80000000 71 #define SDRAM_CFG_BI 0x00000001 72 73 #ifdef CONFIG_RAMBOOT_PBL 74 #define CONFIG_SYS_FSL_PBL_PBI \ 75 board/freescale/ls1021aiot/ls102xa_pbi.cfg 76 #endif 77 78 #ifdef CONFIG_SD_BOOT 79 #define CONFIG_SYS_FSL_PBL_RCW \ 80 board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg 81 #define CONFIG_SPL_FRAMEWORK 82 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 83 #define CONFIG_SPL_LIBCOMMON_SUPPORT 84 #define CONFIG_SPL_LIBGENERIC_SUPPORT 85 #define CONFIG_SPL_ENV_SUPPORT 86 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 87 #define CONFIG_SPL_I2C_SUPPORT 88 #define CONFIG_SPL_WATCHDOG_SUPPORT 89 #define CONFIG_SPL_SERIAL_SUPPORT 90 #define CONFIG_SPL_MMC_SUPPORT 91 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 92 93 #define CONFIG_SPL_TEXT_BASE 0x10000000 94 #define CONFIG_SPL_MAX_SIZE 0x1a000 95 #define CONFIG_SPL_STACK 0x1001d000 96 #define CONFIG_SPL_PAD_TO 0x1c000 97 #define CONFIG_SYS_TEXT_BASE 0x82000000 98 99 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ 100 CONFIG_SYS_MONITOR_LEN) 101 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 102 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 103 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 104 #define CONFIG_SYS_MONITOR_LEN 0x80000 105 #endif 106 107 #ifdef CONFIG_QSPI_BOOT 108 #define CONFIG_SYS_TEXT_BASE 0x40010000 109 #endif 110 111 #define CONFIG_NR_DRAM_BANKS 1 112 113 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 114 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 115 116 /* 117 * Serial Port 118 */ 119 #define CONFIG_CONS_INDEX 1 120 #define CONFIG_SYS_NS16550_SERIAL 121 #define CONFIG_SYS_NS16550_REG_SIZE 1 122 #define CONFIG_SYS_NS16550_CLK get_serial_clock() 123 124 /* 125 * I2C 126 */ 127 #define CONFIG_CMD_I2C 128 #define CONFIG_SYS_I2C 129 #define CONFIG_SYS_I2C_MXC 130 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 131 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 132 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 133 134 /* EEPROM */ 135 #define CONFIG_ID_EEPROM 136 #define CONFIG_SYS_I2C_EEPROM_NXID 137 #define CONFIG_SYS_EEPROM_BUS_NUM 0 138 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 139 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 140 141 /* 142 * MMC 143 */ 144 #define CONFIG_CMD_MMC 145 #define CONFIG_FSL_ESDHC 146 147 /* SATA */ 148 #define CONFIG_CMD_SCSI 149 #define CONFIG_LIBATA 150 #define CONFIG_SCSI_AHCI 151 #define CONFIG_SCSI_AHCI_PLAT 152 #ifndef PCI_DEVICE_ID_FREESCALE_AHCI 153 #define PCI_DEVICE_ID_FREESCALE_AHCI 0x0440 154 #endif 155 #define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_FREESCALE, \ 156 PCI_DEVICE_ID_FREESCALE_AHCI} 157 158 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 159 #define CONFIG_SYS_SCSI_MAX_LUN 1 160 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 161 CONFIG_SYS_SCSI_MAX_LUN) 162 163 #define CONFIG_CMD_FAT 164 165 /* SPI */ 166 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) 167 #define CONFIG_SPI_FLASH_SPANSION 168 169 /* QSPI */ 170 #define QSPI0_AMBA_BASE 0x40000000 171 #define FSL_QSPI_FLASH_SIZE (1 << 24) 172 #define FSL_QSPI_FLASH_NUM 2 173 #define CONFIG_SPI_FLASH_BAR 174 #define CONFIG_SPI_FLASH_SPANSION 175 #endif 176 177 /* DM SPI */ 178 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) 179 #define CONFIG_CMD_SF 180 #define CONFIG_DM_SPI_FLASH 181 #endif 182 183 /* 184 * eTSEC 185 */ 186 #define CONFIG_TSEC_ENET 187 188 #ifdef CONFIG_TSEC_ENET 189 #define CONFIG_MII 190 #define CONFIG_MII_DEFAULT_TSEC 1 191 #define CONFIG_TSEC1 1 192 #define CONFIG_TSEC1_NAME "eTSEC1" 193 #define CONFIG_TSEC2 1 194 #define CONFIG_TSEC2_NAME "eTSEC2" 195 196 #define TSEC1_PHY_ADDR 1 197 #define TSEC2_PHY_ADDR 3 198 199 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 200 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 201 202 #define TSEC1_PHYIDX 0 203 #define TSEC2_PHYIDX 0 204 205 #define CONFIG_ETHPRIME "eTSEC2" 206 207 #define CONFIG_PHY_GIGE 208 #define CONFIG_PHYLIB 209 #define CONFIG_PHY_ATHEROS 210 211 #define CONFIG_HAS_ETH0 212 #define CONFIG_HAS_ETH1 213 #define CONFIG_HAS_ETH2 214 #endif 215 216 /* PCIe */ 217 #define CONFIG_PCIE1 /* PCIE controler 1 */ 218 #define CONFIG_PCIE2 /* PCIE controler 2 */ 219 220 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" 221 222 #ifdef CONFIG_PCI 223 #define CONFIG_PCI_SCAN_SHOW 224 #define CONFIG_CMD_PCI 225 #endif 226 227 #define CONFIG_CMD_PING 228 #define CONFIG_CMD_DHCP 229 #define CONFIG_CMD_MII 230 231 #define CONFIG_CMDLINE_TAG 232 #define CONFIG_CMDLINE_EDITING 233 234 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT) 235 #undef CONFIG_CMD_IMLS 236 #endif 237 238 #define CONFIG_PEN_ADDR_BIG_ENDIAN 239 #define CONFIG_LAYERSCAPE_NS_ACCESS 240 #define CONFIG_SMP_PEN_ADDR 0x01ee0200 241 #define COUNTER_FREQUENCY 12500000 242 243 #define CONFIG_HWCONFIG 244 #define HWCONFIG_BUFFER_SIZE 256 245 246 #define CONFIG_FSL_DEVICE_DISABLE 247 248 #define CONFIG_EXTRA_ENV_SETTINGS \ 249 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ 250 "initrd_high=0xffffffff\0" \ 251 "fdt_high=0xffffffff\0" 252 253 /* 254 * Miscellaneous configurable options 255 */ 256 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 257 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 258 #define CONFIG_AUTO_COMPLETE 259 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 260 #define CONFIG_SYS_PBSIZE \ 261 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 262 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 263 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 264 265 #define CONFIG_CMD_GREPENV 266 #define CONFIG_CMD_MEMINFO 267 268 #define CONFIG_SYS_LOAD_ADDR 0x82000000 269 270 #define CONFIG_LS102XA_STREAM_ID 271 272 #define CONFIG_SYS_INIT_SP_OFFSET \ 273 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 274 #define CONFIG_SYS_INIT_SP_ADDR \ 275 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 276 277 #ifdef CONFIG_SPL_BUILD 278 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 279 #else 280 /* start of monitor */ 281 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 282 #endif 283 284 #define CONFIG_SYS_QE_FW_ADDR 0x67f40000 285 286 /* 287 * Environment 288 */ 289 290 #define CONFIG_ENV_OVERWRITE 291 292 #if defined(CONFIG_SD_BOOT) 293 #define CONFIG_ENV_OFFSET 0x100000 294 #define CONFIG_ENV_IS_IN_MMC 295 #define CONFIG_SYS_MMC_ENV_DEV 0 296 #define CONFIG_ENV_SIZE 0x2000 297 #elif defined(CONFIG_QSPI_BOOT) 298 #define CONFIG_ENV_IS_IN_SPI_FLASH 299 #define CONFIG_ENV_SIZE 0x2000 300 #define CONFIG_ENV_OFFSET 0x100000 301 #define CONFIG_ENV_SECT_SIZE 0x10000 302 #endif 303 304 #define CONFIG_OF_BOARD_SETUP 305 #define CONFIG_OF_STDOUT_VIA_ALIAS 306 #define CONFIG_CMD_BOOTZ 307 308 #define CONFIG_MISC_INIT_R 309 310 /* Hash command with SHA acceleration supported in hardware */ 311 312 #ifdef CONFIG_FSL_CAAM 313 314 #define CONFIG_CMD_HASH 315 316 #define CONFIG_SHA_HW_ACCEL 317 318 #endif 319 320 #include <asm/fsl_secure_boot.h> 321 322 #endif 323