1 /* 2 * Copyright 2016 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1012ARDB_H__ 8 #define __LS1012ARDB_H__ 9 10 #include "ls1012a_common.h" 11 12 /* DDR */ 13 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 14 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 15 #define CONFIG_NR_DRAM_BANKS 2 16 #define CONFIG_SYS_SDRAM_SIZE 0x40000000 17 #define CONFIG_CMD_MEMINFO 18 #define CONFIG_CMD_MEMTEST 19 #define CONFIG_SYS_MEMTEST_START 0x80000000 20 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 21 22 /* 23 * USB 24 */ 25 #define CONFIG_HAS_FSL_XHCI_USB 26 27 #ifdef CONFIG_HAS_FSL_XHCI_USB 28 #define CONFIG_USB_XHCI_FSL 29 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 30 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 31 #endif 32 33 /* 34 * I2C IO expander 35 */ 36 37 #define I2C_MUX_IO1_ADDR 0x24 38 #define __SW_BOOT_MASK 0xFC 39 #define __SW_BOOT_EMU 0x10 40 #define __SW_BOOT_BANK1 0x00 41 #define __SW_BOOT_BANK2 0x01 42 #define __SW_REV_MASK 0x07 43 #define __SW_REV_A 0xF8 44 #define __SW_REV_B 0xF0 45 46 /* MMC */ 47 #define CONFIG_MMC 48 #ifdef CONFIG_MMC 49 #define CONFIG_FSL_ESDHC 50 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 51 #define CONFIG_GENERIC_MMC 52 #define CONFIG_DOS_PARTITION 53 #endif 54 55 /* SATA */ 56 #define CONFIG_LIBATA 57 #define CONFIG_SCSI 58 #define CONFIG_SCSI_AHCI 59 #define CONFIG_SCSI_AHCI_PLAT 60 #define CONFIG_CMD_SCSI 61 #define CONFIG_DOS_PARTITION 62 #define CONFIG_BOARD_LATE_INIT 63 64 #define CONFIG_SYS_SATA AHCI_BASE_ADDR 65 66 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 67 #define CONFIG_SYS_SCSI_MAX_LUN 1 68 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 69 CONFIG_SYS_SCSI_MAX_LUN) 70 #define CONFIG_PCI /* Enable PCI/PCIE */ 71 #define CONFIG_PCIE1 /* PCIE controller 1 */ 72 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ 73 #define FSL_PCIE_COMPAT "fsl,ls1043a-pcie" 74 75 #define CONFIG_SYS_PCI_64BIT 76 77 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 78 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ 79 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 80 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ 81 82 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000 83 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 84 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ 85 86 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 87 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 88 #define CONFIG_SYS_PCIE_MEM_SIZE 0x80000000 /* 128M */ 89 90 #define CONFIG_NET_MULTI 91 #define CONFIG_PCI_PNP 92 #define CONFIG_PCI_SCAN_SHOW 93 #define CONFIG_CMD_PCI 94 95 #define CONFIG_CMD_MEMINFO 96 #define CONFIG_CMD_MEMTEST 97 #define CONFIG_SYS_MEMTEST_START 0x80000000 98 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 99 100 #endif /* __LS1012ARDB_H__ */ 101