1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2016 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __LS1012AQDS_H__ 7 #define __LS1012AQDS_H__ 8 9 #include "ls1012a_common.h" 10 11 /* DDR */ 12 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 13 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 14 #define CONFIG_NR_DRAM_BANKS 2 15 #define CONFIG_SYS_SDRAM_SIZE 0x40000000 16 #define CONFIG_CMD_MEMINFO 17 #define CONFIG_SYS_MEMTEST_START 0x80000000 18 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 19 20 /* 21 * QIXIS Definitions 22 */ 23 #define CONFIG_FSL_QIXIS 24 25 #ifdef CONFIG_FSL_QIXIS 26 #define CONFIG_QIXIS_I2C_ACCESS 27 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 28 #define QIXIS_LBMAP_BRDCFG_REG 0x04 29 #define QIXIS_LBMAP_SWITCH 6 30 #define QIXIS_LBMAP_MASK 0x08 31 #define QIXIS_LBMAP_SHIFT 0 32 #define QIXIS_LBMAP_DFLTBANK 0x00 33 #define QIXIS_LBMAP_ALTBANK 0x08 34 #define QIXIS_RST_CTL_RESET 0x31 35 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 36 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 37 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 38 #endif 39 40 /* 41 * I2C bus multiplexer 42 */ 43 #define I2C_MUX_PCA_ADDR_PRI 0x77 44 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 45 #define I2C_RETIMER_ADDR 0x18 46 #define I2C_MUX_CH_DEFAULT 0x8 47 #define I2C_MUX_CH_CH7301 0xC 48 #define I2C_MUX_CH5 0xD 49 #define I2C_MUX_CH7 0xF 50 51 #define I2C_MUX_CH_VOL_MONITOR 0xa 52 53 /* 54 * RTC configuration 55 */ 56 #define RTC 57 #define CONFIG_RTC_PCF8563 1 58 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ 59 60 /* EEPROM */ 61 #define CONFIG_ID_EEPROM 62 #define CONFIG_SYS_I2C_EEPROM_NXID 63 #define CONFIG_SYS_EEPROM_BUS_NUM 0 64 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 65 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 66 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 67 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 68 69 70 /* Voltage monitor on channel 2*/ 71 #define I2C_VOL_MONITOR_ADDR 0x40 72 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 73 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 74 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 75 76 /* DSPI */ 77 #define CONFIG_FSL_DSPI1 78 #define CONFIG_DEFAULT_SPI_BUS 1 79 80 #define CONFIG_CMD_SPI 81 #define MMAP_DSPI DSPI1_BASE_ADDR 82 83 #define CONFIG_SYS_DSPI_CTAR0 1 84 85 #define CONFIG_SYS_DSPI_CTAR1 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\ 86 DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \ 87 DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \ 88 DSPI_CTAR_DT(0)) 89 #define CONFIG_SPI_FLASH_SST /* cs1 */ 90 91 #define CONFIG_SYS_DSPI_CTAR2 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\ 92 DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \ 93 DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \ 94 DSPI_CTAR_DT(0)) 95 #define CONFIG_SPI_FLASH_STMICRO /* cs2 */ 96 97 #define CONFIG_SYS_DSPI_CTAR3 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\ 98 DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \ 99 DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \ 100 DSPI_CTAR_DT(0)) 101 #define CONFIG_SPI_FLASH_EON /* cs3 */ 102 103 #define CONFIG_SF_DEFAULT_SPEED 10000000 104 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 105 #define CONFIG_SF_DEFAULT_BUS 1 106 #define CONFIG_SF_DEFAULT_CS 0 107 108 /* MMC */ 109 #ifdef CONFIG_MMC 110 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 111 #endif 112 113 #define CONFIG_PCIE1 /* PCIE controller 1 */ 114 115 #define CONFIG_PCI_SCAN_SHOW 116 117 #define CONFIG_CMD_MEMINFO 118 #define CONFIG_SYS_MEMTEST_START 0x80000000 119 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 120 121 #define CONFIG_MISC_INIT_R 122 123 #endif /* __LS1012AQDS_H__ */ 124