1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2016 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __LS1012AQDS_H__ 7 #define __LS1012AQDS_H__ 8 9 #include "ls1012a_common.h" 10 11 /* DDR */ 12 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 13 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 14 #define CONFIG_SYS_SDRAM_SIZE 0x40000000 15 #define CONFIG_CMD_MEMINFO 16 #define CONFIG_SYS_MEMTEST_START 0x80000000 17 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 18 19 /* 20 * QIXIS Definitions 21 */ 22 #define CONFIG_FSL_QIXIS 23 24 #ifdef CONFIG_FSL_QIXIS 25 #define CONFIG_QIXIS_I2C_ACCESS 26 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 27 #define QIXIS_LBMAP_BRDCFG_REG 0x04 28 #define QIXIS_LBMAP_SWITCH 6 29 #define QIXIS_LBMAP_MASK 0x08 30 #define QIXIS_LBMAP_SHIFT 0 31 #define QIXIS_LBMAP_DFLTBANK 0x00 32 #define QIXIS_LBMAP_ALTBANK 0x08 33 #define QIXIS_RST_CTL_RESET 0x31 34 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 35 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 36 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 37 #endif 38 39 /* 40 * I2C bus multiplexer 41 */ 42 #define I2C_MUX_PCA_ADDR_PRI 0x77 43 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ 44 #define I2C_RETIMER_ADDR 0x18 45 #define I2C_MUX_CH_DEFAULT 0x8 46 #define I2C_MUX_CH_CH7301 0xC 47 #define I2C_MUX_CH5 0xD 48 #define I2C_MUX_CH7 0xF 49 50 #define I2C_MUX_CH_VOL_MONITOR 0xa 51 52 /* 53 * RTC configuration 54 */ 55 #define RTC 56 #define CONFIG_RTC_PCF8563 1 57 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ 58 59 /* EEPROM */ 60 #define CONFIG_ID_EEPROM 61 #define CONFIG_SYS_I2C_EEPROM_NXID 62 #define CONFIG_SYS_EEPROM_BUS_NUM 0 63 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 64 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 65 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 66 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 67 68 69 /* Voltage monitor on channel 2*/ 70 #define I2C_VOL_MONITOR_ADDR 0x40 71 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 72 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 73 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 74 75 /* DSPI */ 76 #define CONFIG_FSL_DSPI1 77 78 #define MMAP_DSPI DSPI1_BASE_ADDR 79 80 #define CONFIG_SYS_DSPI_CTAR0 1 81 82 #define CONFIG_SYS_DSPI_CTAR1 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\ 83 DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \ 84 DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \ 85 DSPI_CTAR_DT(0)) 86 #define CONFIG_SPI_FLASH_SST /* cs1 */ 87 88 #define CONFIG_SYS_DSPI_CTAR2 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\ 89 DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \ 90 DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \ 91 DSPI_CTAR_DT(0)) 92 #define CONFIG_SPI_FLASH_STMICRO /* cs2 */ 93 94 #define CONFIG_SYS_DSPI_CTAR3 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\ 95 DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \ 96 DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \ 97 DSPI_CTAR_DT(0)) 98 #define CONFIG_SPI_FLASH_EON /* cs3 */ 99 100 /* MMC */ 101 #ifdef CONFIG_MMC 102 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 103 #endif 104 105 #define CONFIG_PCIE1 /* PCIE controller 1 */ 106 107 #define CONFIG_PCI_SCAN_SHOW 108 109 #define CONFIG_CMD_MEMINFO 110 #define CONFIG_SYS_MEMTEST_START 0x80000000 111 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 112 113 #include <asm/fsl_secure_boot.h> 114 #endif /* __LS1012AQDS_H__ */ 115