1ff78aa2bSPrabhakar Kushwaha /* 2ff78aa2bSPrabhakar Kushwaha * Copyright 2016 Freescale Semiconductor, Inc. 3ff78aa2bSPrabhakar Kushwaha * 4ff78aa2bSPrabhakar Kushwaha * SPDX-License-Identifier: GPL-2.0+ 5ff78aa2bSPrabhakar Kushwaha */ 6ff78aa2bSPrabhakar Kushwaha 7ff78aa2bSPrabhakar Kushwaha #ifndef __LS1012ARDB_H__ 8ff78aa2bSPrabhakar Kushwaha #define __LS1012ARDB_H__ 9ff78aa2bSPrabhakar Kushwaha 10ff78aa2bSPrabhakar Kushwaha #include "ls1012a_common.h" 11ff78aa2bSPrabhakar Kushwaha 12*b9e745bbSShengzhou Liu /* DDR */ 13ff78aa2bSPrabhakar Kushwaha #define CONFIG_DIMM_SLOTS_PER_CTLR 1 14ff78aa2bSPrabhakar Kushwaha #define CONFIG_CHIP_SELECTS_PER_CTRL 1 15ff78aa2bSPrabhakar Kushwaha #define CONFIG_NR_DRAM_BANKS 2 16ff78aa2bSPrabhakar Kushwaha #define CONFIG_SYS_SDRAM_SIZE 0x20000000 17*b9e745bbSShengzhou Liu #define CONFIG_CHIP_SELECTS_PER_CTRL 1 18ff78aa2bSPrabhakar Kushwaha #define CONFIG_CMD_MEMINFO 19ff78aa2bSPrabhakar Kushwaha #define CONFIG_CMD_MEMTEST 20ff78aa2bSPrabhakar Kushwaha #define CONFIG_SYS_MEMTEST_START 0x80000000 21ff78aa2bSPrabhakar Kushwaha #define CONFIG_SYS_MEMTEST_END 0x9fffffff 22ff78aa2bSPrabhakar Kushwaha 23*b9e745bbSShengzhou Liu /* DDR board-specific timing parameters */ 24*b9e745bbSShengzhou Liu #define CONFIG_MMDC_MDCTL 0x04180000 25*b9e745bbSShengzhou Liu #define CONFIG_MMDC_MDPDC 0x00030035 26*b9e745bbSShengzhou Liu #define CONFIG_MMDC_MDOTC 0x12554000 27*b9e745bbSShengzhou Liu #define CONFIG_MMDC_MDCFG0 0xbabf7954 28*b9e745bbSShengzhou Liu #define CONFIG_MMDC_MDCFG1 0xdb328f64 29*b9e745bbSShengzhou Liu #define CONFIG_MMDC_MDCFG2 0x01ff00db 30*b9e745bbSShengzhou Liu #define CONFIG_MMDC_MDMISC 0x00001680 31*b9e745bbSShengzhou Liu #define CONFIG_MMDC_MDREF 0x0f3c8000 32*b9e745bbSShengzhou Liu #define CONFIG_MMDC_MDRWD 0x00002000 33*b9e745bbSShengzhou Liu #define CONFIG_MMDC_MDOR 0x00bf1023 34*b9e745bbSShengzhou Liu #define CONFIG_MMDC_MDASP 0x0000003f 35*b9e745bbSShengzhou Liu #define CONFIG_MMDC_MPODTCTRL 0x0000022a 36*b9e745bbSShengzhou Liu #define CONFIG_MMDC_MPZQHWCTRL 0xa1390003 37*b9e745bbSShengzhou Liu 38*b9e745bbSShengzhou Liu 39ff78aa2bSPrabhakar Kushwaha /* 40ff78aa2bSPrabhakar Kushwaha * USB 41ff78aa2bSPrabhakar Kushwaha */ 42ff78aa2bSPrabhakar Kushwaha #define CONFIG_HAS_FSL_XHCI_USB 43ff78aa2bSPrabhakar Kushwaha 44ff78aa2bSPrabhakar Kushwaha #ifdef CONFIG_HAS_FSL_XHCI_USB 45ff78aa2bSPrabhakar Kushwaha #define CONFIG_USB_XHCI_FSL 46ff78aa2bSPrabhakar Kushwaha #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 47ff78aa2bSPrabhakar Kushwaha #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 48ff78aa2bSPrabhakar Kushwaha #endif 49ff78aa2bSPrabhakar Kushwaha 50ff78aa2bSPrabhakar Kushwaha #define CONFIG_CMD_MEMINFO 51ff78aa2bSPrabhakar Kushwaha #define CONFIG_CMD_MEMTEST 52ff78aa2bSPrabhakar Kushwaha #define CONFIG_SYS_MEMTEST_START 0x80000000 53ff78aa2bSPrabhakar Kushwaha #define CONFIG_SYS_MEMTEST_END 0x9fffffff 54ff78aa2bSPrabhakar Kushwaha 55ff78aa2bSPrabhakar Kushwaha #endif /* __LS1012ARDB_H__ */ 56