1 /* 2 * Copyright 2016 Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __LS1012A_COMMON_H 8 #define __LS1012A_COMMON_H 9 10 #define CONFIG_FSL_LAYERSCAPE 11 #define CONFIG_GICV2 12 13 #include <asm/arch/config.h> 14 #define CONFIG_SYS_NO_FLASH 15 16 #define CONFIG_SUPPORT_RAW_INITRD 17 18 #define CONFIG_DISPLAY_BOARDINFO_LATE 19 20 #define CONFIG_SYS_TEXT_BASE 0x40100000 21 22 #define CONFIG_SYS_CLK_FREQ 125000000 23 24 #define CONFIG_SKIP_LOWLEVEL_INIT 25 #define CONFIG_BOARD_EARLY_INIT_F 1 26 27 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 28 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 29 30 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 31 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 32 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 33 34 /* Generic Timer Definitions */ 35 #define COUNTER_FREQUENCY CONFIG_SYS_CLK_FREQ/4 /* 25MHz */ 36 37 /* CSU */ 38 #define CONFIG_LAYERSCAPE_NS_ACCESS 39 40 /* Size of malloc() pool */ 41 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) 42 43 /*SPI device */ 44 #ifdef CONFIG_QSPI_BOOT 45 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 46 #define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 47 #define CONFIG_ENV_SPI_BUS 0 48 #define CONFIG_ENV_SPI_CS 0 49 #define CONFIG_ENV_SPI_MAX_HZ 1000000 50 #define CONFIG_ENV_SPI_MODE 0x03 51 #define CONFIG_SPI_FLASH_SPANSION 52 #define CONFIG_FSL_SPI_INTERFACE 53 #define CONFIG_SF_DATAFLASH 54 55 #define CONFIG_FSL_QSPI 56 #define QSPI0_AMBA_BASE 0x40000000 57 #define CONFIG_SPI_FLASH_SPANSION 58 #define CONFIG_SPI_FLASH_BAR 59 60 #define FSL_QSPI_FLASH_SIZE (1 << 24) 61 #define FSL_QSPI_FLASH_NUM 2 62 63 /* 64 * Environment 65 */ 66 #define CONFIG_ENV_OVERWRITE 67 68 #define CONFIG_ENV_IS_IN_SPI_FLASH 69 #define CONFIG_ENV_SIZE 0x40000 /* 256KB */ 70 #define CONFIG_ENV_OFFSET 0x200000 /* 2MB */ 71 #define CONFIG_ENV_SECT_SIZE 0x40000 72 #endif 73 74 /* I2C */ 75 #define CONFIG_SYS_I2C 76 #define CONFIG_SYS_I2C_MXC 77 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 78 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 79 80 #define CONFIG_CONS_INDEX 1 81 #define CONFIG_SYS_NS16550_SERIAL 82 #define CONFIG_SYS_NS16550_REG_SIZE 1 83 #define CONFIG_SYS_NS16550_CLK (get_serial_clock()) 84 85 #define CONFIG_BAUDRATE 115200 86 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 87 88 /* Command line configuration */ 89 #define CONFIG_CMD_ENV 90 #undef CONFIG_CMD_IMLS 91 92 #define CONFIG_ARCH_EARLY_INIT_R 93 94 #define CONFIG_SYS_HZ 1000 95 96 #define CONFIG_HWCONFIG 97 #define HWCONFIG_BUFFER_SIZE 128 98 99 /* Initial environment variables */ 100 #define CONFIG_EXTRA_ENV_SETTINGS \ 101 "verify=no\0" \ 102 "loadaddr=0x80100000\0" \ 103 "kernel_addr=0x100000\0" \ 104 "fdt_high=0xffffffffffffffff\0" \ 105 "initrd_high=0xffffffffffffffff\0" \ 106 "kernel_start=0xa00000\0" \ 107 "kernel_load=0xa0000000\0" \ 108 "kernel_size=0x2800000\0" \ 109 110 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ 111 "earlycon=uart8250,mmio,0x21c0500 quiet lpj=250000" 112 #define CONFIG_BOOTCOMMAND "sf probe 0:0; sf read $kernel_load "\ 113 "$kernel_start $kernel_size && "\ 114 "bootm $kernel_load" 115 116 /* Monitor Command Prompt */ 117 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 118 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 119 sizeof(CONFIG_SYS_PROMPT) + 16) 120 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ 121 #define CONFIG_SYS_LONGHELP 122 #define CONFIG_CMDLINE_EDITING 1 123 #define CONFIG_AUTO_COMPLETE 124 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 125 126 #define CONFIG_PANIC_HANG 127 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 128 129 #include <asm/fsl_secure_boot.h> 130 131 #endif /* __LS1012A_COMMON_H */ 132