1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2016 David Lechner <david@lechnology.com> 4 * 5 * Based on da850evm.h 6 * 7 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 8 * 9 * Based on davinci_dvevm.h. Original Copyrights follow: 10 * 11 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 12 */ 13 14 #ifndef __CONFIG_H 15 #define __CONFIG_H 16 17 /* 18 * SoC Configuration 19 */ 20 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH 21 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) 22 #define CONFIG_SYS_OSCIN_FREQ 24000000 23 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE 24 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) 25 26 /* 27 * Memory Info 28 */ 29 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ 30 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ 31 #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ 32 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ 33 34 /* memtest start addr */ 35 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) 36 37 /* memtest will be run on 16MB */ 38 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) 39 40 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ 41 42 /* 43 * Serial Driver info 44 */ 45 #define CONFIG_SYS_NS16550_SERIAL 46 #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ 47 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART1_BASE /* Base address of UART1 */ 48 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) 49 50 #define CONFIG_SYS_SPI_BASE DAVINCI_SPI0_BASE 51 #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID) 52 #define CONFIG_SF_DEFAULT_SPEED 50000000 53 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 54 55 /* 56 * I2C Configuration 57 */ 58 #define CONFIG_SYS_I2C 59 #define CONFIG_SYS_I2C_DAVINCI 60 #define CONFIG_SYS_DAVINCI_I2C_SPEED 400000 61 #define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ 62 63 /* 64 * U-Boot general configuration 65 */ 66 #define CONFIG_BOOTFILE "uImage" /* Boot file name */ 67 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 68 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ 69 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) 70 #define CONFIG_MX_CYCLIC 71 72 /* 73 * Linux Information 74 */ 75 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) 76 #define CONFIG_HWCONFIG /* enable hwconfig */ 77 #define CONFIG_CMDLINE_TAG 78 #define CONFIG_REVISION_TAG 79 #define CONFIG_SERIAL_TAG 80 #define CONFIG_SETUP_MEMORY_TAGS 81 #define CONFIG_SETUP_INITRD_TAG 82 #define CONFIG_BOOTCOMMAND \ 83 "if mmc rescan; then " \ 84 "if run loadbootscr; then " \ 85 "run bootscript; " \ 86 "else " \ 87 "if run loadbootenv; then " \ 88 "echo Loaded env from ${bootenvfile};" \ 89 "run importbootenv;" \ 90 "fi;" \ 91 "if test -n $uenvcmd; then " \ 92 "echo Running uenvcmd...;" \ 93 "run uenvcmd;" \ 94 "fi;" \ 95 "if run loadimage; then " \ 96 "run mmcargs; " \ 97 "if run loadfdt; then " \ 98 "echo Using ${fdtfile}...;" \ 99 "run fdtfixup; " \ 100 "run fdtboot; "\ 101 "fi; " \ 102 "run mmcboot; " \ 103 "fi; " \ 104 "fi; " \ 105 "fi; "\ 106 "run flashargs; " \ 107 "run flashboot" 108 #define CONFIG_EXTRA_ENV_SETTINGS \ 109 "bootenvfile=uEnv.txt\0" \ 110 "fdtfile=da850-lego-ev3.dtb\0" \ 111 "memsize=64M\0" \ 112 "filesyssize=10M\0" \ 113 "verify=n\0" \ 114 "console=ttyS1,115200n8\0" \ 115 "bootscraddr=0xC0600000\0" \ 116 "fdtaddr=0xC0600000\0" \ 117 "loadaddr=0xC0007FC0\0" \ 118 "filesysaddr=0xC1180000\0" \ 119 "fwupdateboot=mw 0xFFFF1FFC 0x5555AAAA; reset\0" \ 120 "importbootenv=echo Importing environment...; " \ 121 "env import -t ${loadaddr} ${filesize}\0" \ 122 "loadbootenv=fatload mmc 0 ${loadaddr} ${bootenvfile}\0" \ 123 "mmcargs=setenv bootargs console=${console} root=/dev/mmcblk0p2 rw " \ 124 "rootwait ${optargs}\0" \ 125 "mmcboot=bootm ${loadaddr}\0" \ 126 "flashargs=setenv bootargs initrd=${filesysaddr},${filesyssize} " \ 127 "root=/dev/ram0 rw rootfstype=squashfs console=${console} " \ 128 "${optargs}\0" \ 129 "flashboot=sf probe 0; " \ 130 "sf read ${fdtaddr} 0x40000 0x10000; " \ 131 "sf read ${loadaddr} 0x50000 0x400000; " \ 132 "sf read ${filesysaddr} 0x450000 0xA00000; " \ 133 "run fdtfixup; " \ 134 "run fdtboot\0" \ 135 "loadimage=fatload mmc 0 ${loadaddr} uImage\0" \ 136 "loadfdt=fatload mmc 0 ${fdtaddr} ${fdtfile}\0" \ 137 "fdtfixup=fdt addr ${fdtaddr}; fdt resize; fdt chosen\0" \ 138 "fdtboot=bootm ${loadaddr} - ${fdtaddr}\0" \ 139 "loadbootscr=fatload mmc 0 ${bootscraddr} boot.scr\0" \ 140 "bootscript=source ${bootscraddr}\0" 141 142 #ifdef CONFIG_CMD_BDI 143 #define CONFIG_CLOCKS 144 #endif 145 146 #define CONFIG_ENV_SIZE (16 << 10) 147 148 /* additions for new relocation code, must added to all boards */ 149 #define CONFIG_SYS_SDRAM_BASE 0xc0000000 150 151 #define CONFIG_SYS_INIT_SP_ADDR 0x80010000 152 153 #include <asm/arch/hardware.h> 154 155 #endif /* __CONFIG_H */ 156