1 /* 2 * Copyright (C) 2016 David Lechner <david@lechnology.com> 3 * 4 * Based on da850evm.h 5 * 6 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 7 * 8 * Based on davinci_dvevm.h. Original Copyrights follow: 9 * 10 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14 15 #ifndef __CONFIG_H 16 #define __CONFIG_H 17 18 /* 19 * SoC Configuration 20 */ 21 #define CONFIG_MACH_DAVINCI_DA850_EVM 22 #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ 23 #define CONFIG_SOC_DA850 /* TI DA850 SoC */ 24 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH 25 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) 26 #define CONFIG_SYS_OSCIN_FREQ 24000000 27 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE 28 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) 29 #define CONFIG_SYS_DA850_PLL_INIT 30 #define CONFIG_SYS_DA850_DDR_INIT 31 32 #define CONFIG_SYS_TEXT_BASE 0xc1080000 33 34 35 /* 36 * Memory Info 37 */ 38 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ 39 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ 40 #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ 41 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ 42 43 /* memtest start addr */ 44 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) 45 46 /* memtest will be run on 16MB */ 47 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) 48 49 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ 50 51 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ 52 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ 53 DAVINCI_SYSCFG_SUSPSRC_SPI0 | \ 54 DAVINCI_SYSCFG_SUSPSRC_UART1 | \ 55 DAVINCI_SYSCFG_SUSPSRC_EMAC | \ 56 DAVINCI_SYSCFG_SUSPSRC_I2C) 57 58 /* 59 * PLL configuration 60 */ 61 #define CONFIG_SYS_DV_CLKMODE 0 62 #define CONFIG_SYS_DA850_PLL0_POSTDIV 1 63 #define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000 64 #define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001 65 #define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 66 #define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003 67 #define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002 68 #define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1 69 #define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005 70 71 #define CONFIG_SYS_DA850_PLL1_POSTDIV 1 72 #define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000 73 #define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001 74 #define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002 75 76 #define CONFIG_SYS_DA850_PLL0_PLLM 24 77 #define CONFIG_SYS_DA850_PLL1_PLLM 21 78 79 /* 80 * DDR2 memory configuration 81 */ 82 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ 83 DV_DDR_PHY_EXT_STRBEN | \ 84 (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT)) 85 86 #define CONFIG_SYS_DA850_DDR2_SDBCR ( \ 87 (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \ 88 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ 89 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ 90 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ 91 (0x3 << DV_DDR_SDCR_CL_SHIFT) | \ 92 (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \ 93 (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) 94 95 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ 96 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0 97 98 #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ 99 (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \ 100 (2 << DV_DDR_SDTMR1_RP_SHIFT) | \ 101 (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \ 102 (1 << DV_DDR_SDTMR1_WR_SHIFT) | \ 103 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \ 104 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ 105 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ 106 (0 << DV_DDR_SDTMR1_WTR_SHIFT)) 107 108 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ 109 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ 110 (0 << DV_DDR_SDTMR2_XP_SHIFT) | \ 111 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ 112 (17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ 113 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ 114 (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \ 115 (0 << DV_DDR_SDTMR2_CKE_SHIFT)) 116 117 #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494 118 #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 119 120 /* 121 * Serial Driver info 122 */ 123 #define CONFIG_SYS_NS16550_SERIAL 124 #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ 125 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART1_BASE /* Base address of UART1 */ 126 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) 127 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ 128 #define CONFIG_BAUDRATE 115200 /* Default baud rate */ 129 130 #define CONFIG_SPI 131 #define CONFIG_CMD_SF 132 #define CONFIG_DAVINCI_SPI 133 #define CONFIG_SYS_SPI_BASE DAVINCI_SPI0_BASE 134 #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID) 135 #define CONFIG_SF_DEFAULT_SPEED 50000000 136 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 137 138 /* 139 * I2C Configuration 140 */ 141 #define CONFIG_SYS_I2C 142 #define CONFIG_SYS_I2C_DAVINCI 143 #define CONFIG_SYS_DAVINCI_I2C_SPEED 400000 144 #define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ 145 146 /* 147 * U-Boot general configuration 148 */ 149 #define CONFIG_BOARD_EARLY_INIT_F 150 #define CONFIG_BOOTFILE "uImage" /* Boot file name */ 151 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 152 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 153 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 154 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ 155 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) 156 #define CONFIG_VERSION_VARIABLE 157 #define CONFIG_AUTO_COMPLETE 158 #define CONFIG_SYS_HUSH_PARSER 159 #define CONFIG_CMDLINE_EDITING 160 #define CONFIG_SYS_LONGHELP 161 #define CONFIG_CRC32_VERIFY 162 #define CONFIG_MX_CYCLIC 163 164 /* 165 * Linux Information 166 */ 167 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) 168 #define CONFIG_HWCONFIG /* enable hwconfig */ 169 #define CONFIG_CMDLINE_TAG 170 #define CONFIG_REVISION_TAG 171 #define CONFIG_SERIAL_TAG 172 #define CONFIG_SETUP_MEMORY_TAGS 173 #define CONFIG_SETUP_INITRD_TAG 174 #define CONFIG_BOOTDELAY 0 175 #define CONFIG_ZERO_BOOTDELAY_CHECK 176 #define CONFIG_BOOTCOMMAND \ 177 "if mmc rescan; then " \ 178 "if run loadbootscr; then " \ 179 "run bootscript; " \ 180 "else " \ 181 "if run loadimage; then " \ 182 "run mmcargs; " \ 183 "run mmcboot; " \ 184 "else " \ 185 "run flashargs; " \ 186 "run flashboot; " \ 187 "fi; " \ 188 "fi; " \ 189 "else " \ 190 "run flashargs; " \ 191 "run flashboot; " \ 192 "fi" 193 #define CONFIG_EXTRA_ENV_SETTINGS \ 194 "hostname=EV3\0" \ 195 "memsize=64M\0" \ 196 "filesyssize=10M\0" \ 197 "verify=n\0" \ 198 "console=ttyS1,115200n8\0" \ 199 "bootscraddr=0xC0600000\0" \ 200 "loadaddr=0xC0007FC0\0" \ 201 "filesysaddr=0xC1180000\0" \ 202 "fwupdateboot=mw 0xFFFF1FFC 0x5555AAAA; reset\0" \ 203 "mmcargs=setenv bootargs mem=${memsize} console=${console} root=/dev/mmcblk0p2 rw rootwait lpj=747520\0" \ 204 "mmcboot=bootm ${loadaddr}\0" \ 205 "flashargs=setenv bootargs mem=${memsize} initrd=${filesysaddr},${filesyssize} root=/dev/ram0 rw rootfstype=squashfs console=${console} lpj=747520\0" \ 206 "flashboot=sf probe 0; sf read ${loadaddr} 0x50000 0x300000; sf read ${filesysaddr} 0x350000 0x960000; bootm ${loadaddr}\0" \ 207 "loadimage=fatload mmc 0 ${loadaddr} uImage\0" \ 208 "loadbootscr=fatload mmc 0 ${bootscraddr} boot.scr\0" \ 209 "bootscript=source ${bootscraddr}\0" \ 210 211 /* 212 * U-Boot commands 213 */ 214 #define CONFIG_CMD_ASKENV 215 #define CONFIG_CMD_DHCP 216 #define CONFIG_CMD_DIAG 217 #define CONFIG_CMD_MII 218 #define CONFIG_CMD_PING 219 #define CONFIG_CMD_SAVES 220 221 #ifdef CONFIG_CMD_BDI 222 #define CONFIG_CLOCKS 223 #endif 224 225 #define CONFIG_CMD_SPI 226 227 #define CONFIG_ENV_IS_NOWHERE 228 #define CONFIG_SYS_NO_FLASH 229 #define CONFIG_ENV_SIZE (16 << 10) 230 231 /* SD/MMC configuration */ 232 #define CONFIG_MMC 233 #define CONFIG_DAVINCI_MMC_SD1 234 #define CONFIG_GENERIC_MMC 235 #define CONFIG_DAVINCI_MMC 236 237 /* 238 * Enable MMC commands only when 239 * MMC support is present 240 */ 241 #ifdef CONFIG_MMC 242 #define CONFIG_DOS_PARTITION 243 #define CONFIG_CMD_EXT3 244 #define CONFIG_CMD_EXT4 245 #define CONFIG_CMD_FAT 246 #define CONFIG_CMD_MMC 247 #endif 248 249 /* additions for new relocation code, must added to all boards */ 250 #define CONFIG_SYS_SDRAM_BASE 0xc0000000 251 252 #define CONFIG_SYS_INIT_SP_ADDR 0x80010000 253 254 #endif /* __CONFIG_H */ 255