1 /* 2 * Copyright (C) 2016 David Lechner <david@lechnology.com> 3 * 4 * Based on da850evm.h 5 * 6 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ 7 * 8 * Based on davinci_dvevm.h. Original Copyrights follow: 9 * 10 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14 15 #ifndef __CONFIG_H 16 #define __CONFIG_H 17 18 /* 19 * SoC Configuration 20 */ 21 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH 22 #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) 23 #define CONFIG_SYS_OSCIN_FREQ 24000000 24 #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE 25 #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) 26 27 #define CONFIG_SYS_TEXT_BASE 0xc1080000 28 29 /* 30 * Memory Info 31 */ 32 #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ 33 #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ 34 #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ 35 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ 36 37 /* memtest start addr */ 38 #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) 39 40 /* memtest will be run on 16MB */ 41 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) 42 43 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ 44 45 #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ 46 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ 47 DAVINCI_SYSCFG_SUSPSRC_SPI0 | \ 48 DAVINCI_SYSCFG_SUSPSRC_UART1 | \ 49 DAVINCI_SYSCFG_SUSPSRC_EMAC | \ 50 DAVINCI_SYSCFG_SUSPSRC_I2C) 51 52 /* 53 * PLL configuration 54 */ 55 #define CONFIG_SYS_DV_CLKMODE 0 56 #define CONFIG_SYS_DA850_PLL0_POSTDIV 1 57 #define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000 58 #define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001 59 #define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 60 #define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003 61 #define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002 62 #define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1 63 #define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005 64 65 #define CONFIG_SYS_DA850_PLL1_POSTDIV 1 66 #define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000 67 #define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001 68 #define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002 69 70 #define CONFIG_SYS_DA850_PLL0_PLLM 24 71 #define CONFIG_SYS_DA850_PLL1_PLLM 21 72 73 /* 74 * DDR2 memory configuration 75 */ 76 #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ 77 DV_DDR_PHY_EXT_STRBEN | \ 78 (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT)) 79 80 #define CONFIG_SYS_DA850_DDR2_SDBCR ( \ 81 (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \ 82 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ 83 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ 84 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ 85 (0x3 << DV_DDR_SDCR_CL_SHIFT) | \ 86 (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \ 87 (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) 88 89 /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ 90 #define CONFIG_SYS_DA850_DDR2_SDBCR2 0 91 92 #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ 93 (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \ 94 (2 << DV_DDR_SDTMR1_RP_SHIFT) | \ 95 (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \ 96 (1 << DV_DDR_SDTMR1_WR_SHIFT) | \ 97 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \ 98 (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ 99 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ 100 (0 << DV_DDR_SDTMR1_WTR_SHIFT)) 101 102 #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ 103 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ 104 (0 << DV_DDR_SDTMR2_XP_SHIFT) | \ 105 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ 106 (17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ 107 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ 108 (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \ 109 (0 << DV_DDR_SDTMR2_CKE_SHIFT)) 110 111 #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494 112 #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 113 114 /* 115 * Serial Driver info 116 */ 117 #define CONFIG_SYS_NS16550_SERIAL 118 #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ 119 #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART1_BASE /* Base address of UART1 */ 120 #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) 121 #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ 122 123 #define CONFIG_SPI 124 #define CONFIG_SYS_SPI_BASE DAVINCI_SPI0_BASE 125 #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID) 126 #define CONFIG_SF_DEFAULT_SPEED 50000000 127 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 128 129 /* 130 * I2C Configuration 131 */ 132 #define CONFIG_SYS_I2C 133 #define CONFIG_SYS_I2C_DAVINCI 134 #define CONFIG_SYS_DAVINCI_I2C_SPEED 400000 135 #define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ 136 137 /* 138 * U-Boot general configuration 139 */ 140 #define CONFIG_BOOTFILE "uImage" /* Boot file name */ 141 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 142 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ 143 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) 144 #define CONFIG_AUTO_COMPLETE 145 #define CONFIG_CMDLINE_EDITING 146 #define CONFIG_SYS_LONGHELP 147 #define CONFIG_MX_CYCLIC 148 149 /* 150 * Linux Information 151 */ 152 #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) 153 #define CONFIG_HWCONFIG /* enable hwconfig */ 154 #define CONFIG_CMDLINE_TAG 155 #define CONFIG_REVISION_TAG 156 #define CONFIG_SERIAL_TAG 157 #define CONFIG_SETUP_MEMORY_TAGS 158 #define CONFIG_SETUP_INITRD_TAG 159 #define CONFIG_BOOTCOMMAND \ 160 "if mmc rescan; then " \ 161 "if run loadbootscr; then " \ 162 "run bootscript; " \ 163 "else " \ 164 "if run loadimage; then " \ 165 "run mmcargs; " \ 166 "run mmcboot; " \ 167 "else " \ 168 "run flashargs; " \ 169 "run flashboot; " \ 170 "fi; " \ 171 "fi; " \ 172 "else " \ 173 "run flashargs; " \ 174 "run flashboot; " \ 175 "fi" 176 #define CONFIG_EXTRA_ENV_SETTINGS \ 177 "hostname=EV3\0" \ 178 "memsize=64M\0" \ 179 "filesyssize=10M\0" \ 180 "verify=n\0" \ 181 "console=ttyS1,115200n8\0" \ 182 "bootscraddr=0xC0600000\0" \ 183 "loadaddr=0xC0007FC0\0" \ 184 "filesysaddr=0xC1180000\0" \ 185 "fwupdateboot=mw 0xFFFF1FFC 0x5555AAAA; reset\0" \ 186 "mmcargs=setenv bootargs mem=${memsize} console=${console} root=/dev/mmcblk0p2 rw rootwait lpj=747520\0" \ 187 "mmcboot=bootm ${loadaddr}\0" \ 188 "flashargs=setenv bootargs mem=${memsize} initrd=${filesysaddr},${filesyssize} root=/dev/ram0 rw rootfstype=squashfs console=${console} lpj=747520\0" \ 189 "flashboot=sf probe 0; sf read ${loadaddr} 0x50000 0x300000; sf read ${filesysaddr} 0x350000 0x960000; bootm ${loadaddr}\0" \ 190 "loadimage=fatload mmc 0 ${loadaddr} uImage\0" \ 191 "loadbootscr=fatload mmc 0 ${bootscraddr} boot.scr\0" \ 192 "bootscript=source ${bootscraddr}\0" \ 193 194 #ifdef CONFIG_CMD_BDI 195 #define CONFIG_CLOCKS 196 #endif 197 198 #define CONFIG_ENV_SIZE (16 << 10) 199 200 /* additions for new relocation code, must added to all boards */ 201 #define CONFIG_SYS_SDRAM_BASE 0xc0000000 202 203 #define CONFIG_SYS_INIT_SP_ADDR 0x80010000 204 205 #include <asm/arch/hardware.h> 206 207 #endif /* __CONFIG_H */ 208