1 /* 2 * include/configs/lager.h 3 * This file is lager board configuration. 4 * 5 * Copyright (C) 2013, 2014 Renesas Electronics Corporation 6 * 7 * SPDX-License-Identifier: GPL-2.0 8 */ 9 10 #ifndef __LAGER_H 11 #define __LAGER_H 12 13 #undef DEBUG 14 #define CONFIG_R8A7790 15 #define CONFIG_ARCH_RMOBILE_BOARD_STRING "Lager" 16 17 #include "rcar-gen2-common.h" 18 19 #if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT) 20 #define CONFIG_SYS_TEXT_BASE 0xB0000000 21 #else 22 #define CONFIG_SYS_TEXT_BASE 0xE8080000 23 #endif 24 25 /* STACK */ 26 #if defined(CONFIGF_RMOBILE_EXTRAM_BOOT) 27 #define CONFIG_SYS_INIT_SP_ADDR 0xB003FFFC 28 #else 29 #define CONFIG_SYS_INIT_SP_ADDR 0xE827FFFC 30 #endif 31 #define STACK_AREA_SIZE 0xC000 32 #define LOW_LEVEL_MERAM_STACK \ 33 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) 34 35 /* MEMORY */ 36 #define RCAR_GEN2_SDRAM_BASE 0x40000000 37 #define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024) 38 #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) 39 40 /* SCIF */ 41 42 /* SPI */ 43 #define CONFIG_SPI 44 #define CONFIG_SH_QSPI 45 46 /* SH Ether */ 47 #define CONFIG_SH_ETHER 48 #define CONFIG_SH_ETHER_USE_PORT 0 49 #define CONFIG_SH_ETHER_PHY_ADDR 0x1 50 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII 51 #define CONFIG_SH_ETHER_ALIGNE_SIZE 64 52 #define CONFIG_SH_ETHER_CACHE_WRITEBACK 53 #define CONFIG_SH_ETHER_CACHE_INVALIDATE 54 #define CONFIG_BITBANGMII 55 #define CONFIG_BITBANGMII_MULTI 56 57 /* I2C */ 58 #define CONFIG_SYS_I2C 59 #define CONFIG_SYS_I2C_RCAR 60 #define CONFIG_SYS_RCAR_I2C0_SPEED 400000 61 #define CONFIG_SYS_RCAR_I2C1_SPEED 400000 62 #define CONFIG_SYS_RCAR_I2C2_SPEED 400000 63 #define CONFIG_SYS_RCAR_I2C3_SPEED 400000 64 #define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS 4 65 66 #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ 67 68 /* Board Clock */ 69 #define RMOBILE_XTAL_CLK 20000000u 70 #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK 71 #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ 72 #define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) 73 #define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2) 74 #define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15) 75 #define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12) 76 77 #define CONFIG_SYS_TMU_CLK_DIV 4 78 79 /* USB */ 80 #define CONFIG_USB_EHCI_RMOBILE 81 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 82 83 /* MMC */ 84 #define CONFIG_SH_MMCIF 85 #define CONFIG_SH_MMCIF_ADDR 0xEE220000 86 #define CONFIG_SH_MMCIF_CLK 97500000 87 88 /* Module stop status bits */ 89 /* INTC-RT */ 90 #define CONFIG_SMSTP0_ENA 0x00400000 91 /* MSIF */ 92 #define CONFIG_SMSTP2_ENA 0x00002000 93 /* INTC-SYS, IRQC */ 94 #define CONFIG_SMSTP4_ENA 0x00000180 95 /* SCIF0 */ 96 #define CONFIG_SMSTP7_ENA 0x00200000 97 98 /* SDHI */ 99 #define CONFIG_SH_SDHI_FREQ 97500000 100 101 #endif /* __LAGER_H */ 102