1 /* 2 * include/configs/lager.h 3 * This file is lager board configuration. 4 * 5 * Copyright (C) 2013, 2014 Renesas Electronics Corporation 6 * 7 * SPDX-License-Identifier: GPL-2.0 8 */ 9 10 #ifndef __LAGER_H 11 #define __LAGER_H 12 13 #undef DEBUG 14 #define CONFIG_R8A7790 15 #define CONFIG_RMOBILE_BOARD_STRING "Lager" 16 17 #include "rcar-gen2-common.h" 18 19 #if defined(CONFIG_RMOBILE_EXTRAM_BOOT) 20 #define CONFIG_SYS_TEXT_BASE 0xB0000000 21 #else 22 #define CONFIG_SYS_TEXT_BASE 0xE8080000 23 #endif 24 25 /* STACK */ 26 #if defined(CONFIGF_RMOBILE_EXTRAM_BOOT) 27 #define CONFIG_SYS_INIT_SP_ADDR 0xB003FFFC 28 #else 29 #define CONFIG_SYS_INIT_SP_ADDR 0xE827FFFC 30 #endif 31 #define STACK_AREA_SIZE 0xC000 32 #define LOW_LEVEL_MERAM_STACK \ 33 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) 34 35 /* MEMORY */ 36 #define RCAR_GEN2_SDRAM_BASE 0x40000000 37 #define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024) 38 #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) 39 40 /* SCIF */ 41 #define CONFIG_SCIF_CONSOLE 42 43 /* SPI */ 44 #define CONFIG_SPI 45 #define CONFIG_SPI_FLASH_BAR 46 #define CONFIG_SH_QSPI 47 #define CONFIG_SPI_FLASH 48 #define CONFIG_SPI_FLASH_SPANSION 49 #define CONFIG_SYS_NO_FLASH 50 51 /* SH Ether */ 52 #define CONFIG_NET_MULTI 53 #define CONFIG_SH_ETHER 54 #define CONFIG_SH_ETHER_USE_PORT 0 55 #define CONFIG_SH_ETHER_PHY_ADDR 0x1 56 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII 57 #define CONFIG_SH_ETHER_ALIGNE_SIZE 64 58 #define CONFIG_SH_ETHER_CACHE_WRITEBACK 59 #define CONFIG_SH_ETHER_CACHE_INVALIDATE 60 #define CONFIG_PHYLIB 61 #define CONFIG_PHY_MICREL 62 #define CONFIG_BITBANGMII 63 #define CONFIG_BITBANGMII_MULTI 64 65 /* I2C */ 66 #define CONFIG_SYS_I2C 67 #define CONFIG_SYS_I2C_RCAR 68 #define CONFIG_SYS_RCAR_I2C0_SPEED 400000 69 #define CONFIG_SYS_RCAR_I2C1_SPEED 400000 70 #define CONFIG_SYS_RCAR_I2C2_SPEED 400000 71 #define CONFIG_SYS_RCAR_I2C3_SPEED 400000 72 #define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS 4 73 74 #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ 75 76 /* Board Clock */ 77 #define RMOBILE_XTAL_CLK 20000000u 78 #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK 79 #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ 80 #define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) 81 #define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2) 82 #define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15) 83 #define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12) 84 85 #define CONFIG_SYS_TMU_CLK_DIV 4 86 87 /* USB */ 88 #define CONFIG_USB_EHCI 89 #define CONFIG_USB_EHCI_RMOBILE 90 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 91 #define CONFIG_USB_STORAGE 92 93 /* MMC */ 94 #define CONFIG_MMC 95 #define CONFIG_CMD_MMC 96 #define CONFIG_GENERIC_MMC 97 98 #define CONFIG_SH_MMCIF 99 #define CONFIG_SH_MMCIF_ADDR 0xEE220000 100 #define CONFIG_SH_MMCIF_CLK 97500000 101 102 /* Module stop status bits */ 103 /* INTC-RT */ 104 #define CONFIG_SMSTP0_ENA 0x00400000 105 /* MSIF */ 106 #define CONFIG_SMSTP2_ENA 0x00002000 107 /* INTC-SYS, IRQC */ 108 #define CONFIG_SMSTP4_ENA 0x00000180 109 /* SCIF0 */ 110 #define CONFIG_SMSTP7_ENA 0x00200000 111 112 /* SDHI */ 113 #define CONFIG_SH_SDHI_FREQ 97500000 114 115 #endif /* __LAGER_H */ 116