1 /* 2 * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 3 * Copyright (C) 2012 Renesas Solutions Corp. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __KZM9G_H 9 #define __KZM9G_H 10 11 #undef DEBUG 12 13 #define CONFIG_RMOBILE 14 #define CONFIG_SH73A0 15 #define CONFIG_KZM_A9_GT 16 #define CONFIG_RMOBILE_BOARD_STRING "KMC KZM-A9-GT" 17 #define CONFIG_MACH_TYPE MACH_TYPE_KZM9G 18 19 #include <asm/arch/rmobile.h> 20 21 #define CONFIG_ARCH_CPU_INIT 22 #define CONFIG_DISPLAY_CPUINFO 23 #define CONFIG_DISPLAY_BOARDINFO 24 #define CONFIG_BOARD_EARLY_INIT_F 25 #define CONFIG_L2_OFF 26 #define CONFIG_OF_LIBFDT 27 28 #include <config_cmd_default.h> 29 #define CONFIG_CMDLINE_TAG 30 #define CONFIG_SETUP_MEMORY_TAGS 31 #define CONFIG_INITRD_TAG 32 #define CONFIG_DOS_PARTITION 33 #define CONFIG_CMD_FAT 34 #define CONFIG_CMD_BOOTZ 35 36 #define CONFIG_BAUDRATE 115200 37 #define CONFIG_BOOTARGS "root=/dev/null console=ttySC4,115200" 38 #define CONFIG_BOOTDELAY 3 39 40 #define CONFIG_VERSION_VARIABLE 41 #undef CONFIG_SHOW_BOOT_PROGRESS 42 43 /* MEMORY */ 44 #define KZM_SDRAM_BASE (0x40000000) 45 #define PHYS_SDRAM KZM_SDRAM_BASE 46 #define PHYS_SDRAM_SIZE (512 * 1024 * 1024) 47 #define CONFIG_NR_DRAM_BANKS (1) 48 49 /* NOR Flash */ 50 #define KZM_FLASH_BASE (0x00000000) 51 #define CONFIG_SYS_FLASH_BASE (KZM_FLASH_BASE) 52 #define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT) 53 #define CONFIG_SYS_MAX_FLASH_BANKS (1) 54 #define CONFIG_SYS_MAX_FLASH_SECT (512) 55 56 /* prompt */ 57 #define CONFIG_SYS_LONGHELP 58 #define CONFIG_SYS_PROMPT "KZM-A9-GT# " 59 #define CONFIG_SYS_CBSIZE 256 60 #define CONFIG_SYS_PBSIZE 256 61 #define CONFIG_SYS_MAXARGS 16 62 #define CONFIG_SYS_BARGSIZE 512 63 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 64 65 /* SCIF */ 66 #define CONFIG_SCIF_CONSOLE 67 #define CONFIG_CONS_SCIF4 68 #undef CONFIG_SYS_CONSOLE_INFO_QUIET 69 #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 70 #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE 71 72 #define CONFIG_SYS_MEMTEST_START (KZM_SDRAM_BASE) 73 #define CONFIG_SYS_MEMTEST_END \ 74 (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) 75 #undef CONFIG_SYS_ALT_MEMTEST 76 #undef CONFIG_SYS_MEMTEST_SCRATCH 77 #undef CONFIG_SYS_LOADS_BAUD_CHANGE 78 79 #define CONFIG_SYS_INIT_RAM_ADDR (0xE5600000) /* on MERAM */ 80 #define CONFIG_SYS_INIT_RAM_SIZE (0x10000) 81 #define LOW_LEVEL_MERAM_STACK (CONFIG_SYS_INIT_RAM_ADDR - 4) 82 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 83 CONFIG_SYS_INIT_RAM_SIZE - \ 84 GENERATED_GBL_DATA_SIZE) 85 #define CONFIG_SDRAM_OFFSET_FOR_RT (16 * 1024 * 1024) 86 #define CONFIG_SYS_SDRAM_BASE (KZM_SDRAM_BASE + CONFIG_SDRAM_OFFSET_FOR_RT) 87 #define CONFIG_SYS_SDRAM_SIZE (PHYS_SDRAM_SIZE - CONFIG_SDRAM_OFFSET_FOR_RT) 88 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) 89 90 #define CONFIG_SYS_MONITOR_BASE (KZM_FLASH_BASE) 91 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) 92 #define CONFIG_SYS_GBL_DATA_SIZE (256) 93 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 94 95 #define CONFIG_SYS_TEXT_BASE 0x00000000 96 #define CONFIG_STANDALONE_LOAD_ADDR 0x41000000 97 98 /* FLASH */ 99 #define CONFIG_FLASH_CFI_DRIVER 100 #define CONFIG_SYS_FLASH_CFI 101 #undef CONFIG_SYS_FLASH_QUIET_TEST 102 #define CONFIG_SYS_FLASH_EMPTY_INFO 103 #define FLASH_SECTOR_SIZE (256 * 1024) /* 256 KB sectors */ 104 #define CONFIG_ENV_SIZE FLASH_SECTOR_SIZE 105 #define CONFIG_ENV_OFFSET FLASH_SECTOR_SIZE 106 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) 107 108 /* Timeout for Flash erase operations (in ms) */ 109 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) 110 /* Timeout for Flash write operations (in ms) */ 111 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) 112 /* Timeout for Flash set sector lock bit operations (in ms) */ 113 #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) 114 /* Timeout for Flash clear lock bit operations (in ms) */ 115 #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) 116 117 #undef CONFIG_SYS_FLASH_PROTECTION 118 #undef CONFIG_SYS_DIRECT_FLASH_TFTP 119 #define CONFIG_ENV_IS_IN_FLASH 120 121 /* GPIO / PFC */ 122 #define CONFIG_SH_GPIO_PFC 123 124 /* Clock */ 125 #define CONFIG_GLOBAL_TIMER 126 #define CONFIG_SYS_CLK_FREQ (48000000) 127 #define CONFIG_SYS_CPU_CLK (1196000000) 128 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 129 #define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */ 130 #define CFG_HZ (1000) 131 #define CONFIG_SYS_HZ CFG_HZ 132 133 /* Ether */ 134 #define CONFIG_NET_MULTI 135 #define CONFIG_CMD_PING 136 #define CONFIG_CMD_DHCP 137 #define CONFIG_SMC911X 138 #define CONFIG_SMC911X_BASE (0x10000000) 139 #define CONFIG_SMC911X_32_BIT 140 #define CONFIG_NFS_TIMEOUT 10000UL 141 142 /* I2C */ 143 #define CONFIG_CMD_I2C 144 #define CONFIG_SH_I2C 1 145 #define CONFIG_SH_I2C_8BIT 146 #define CONFIG_HARD_I2C 147 #define CONFIG_I2C_MULTI_BUS 148 #define CONFIG_SYS_MAX_I2C_BUS (5) 149 #define CONFIG_SYS_I2C_MODULE 150 #define CONFIG_SYS_I2C_SPEED (100000) /* 100 kHz */ 151 #define CONFIG_SYS_I2C_SLAVE (0x7F) 152 #define CONFIG_SH_I2C_DATA_HIGH (4) 153 #define CONFIG_SH_I2C_DATA_LOW (5) 154 #define CONFIG_SH_I2C_CLOCK (104000000) /* 104 MHz */ 155 #define CONFIG_SH_I2C_BASE0 (0xE6820000) 156 #define CONFIG_SH_I2C_BASE1 (0xE6822000) 157 #define CONFIG_SH_I2C_BASE2 (0xE6824000) 158 #define CONFIG_SH_I2C_BASE3 (0xE6826000) 159 #define CONFIG_SH_I2C_BASE4 (0xE6828000) 160 161 #endif /* __KZM9G_H */ 162