1 /* 2 * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 3 * Copyright (C) 2012 Renesas Solutions Corp. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __KZM9G_H 9 #define __KZM9G_H 10 11 #undef DEBUG 12 13 #define CONFIG_SH73A0 14 #define CONFIG_KZM_A9_GT 15 #define CONFIG_ARCH_RMOBILE_BOARD_STRING "KMC KZM-A9-GT" 16 #define CONFIG_MACH_TYPE MACH_TYPE_KZM9G 17 18 #include <asm/arch/rmobile.h> 19 20 #define CONFIG_ARCH_CPU_INIT 21 22 #define CONFIG_CMDLINE_TAG 23 #define CONFIG_SETUP_MEMORY_TAGS 24 #define CONFIG_INITRD_TAG 25 26 #undef CONFIG_SHOW_BOOT_PROGRESS 27 28 /* MEMORY */ 29 #define KZM_SDRAM_BASE (0x40000000) 30 #define PHYS_SDRAM KZM_SDRAM_BASE 31 #define PHYS_SDRAM_SIZE (512 * 1024 * 1024) 32 #define CONFIG_NR_DRAM_BANKS (1) 33 34 /* NOR Flash */ 35 #define KZM_FLASH_BASE (0x00000000) 36 #define CONFIG_SYS_FLASH_BASE (KZM_FLASH_BASE) 37 #define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT) 38 #define CONFIG_SYS_MAX_FLASH_BANKS (1) 39 #define CONFIG_SYS_MAX_FLASH_SECT (512) 40 41 /* prompt */ 42 #define CONFIG_SYS_LONGHELP 43 #define CONFIG_SYS_PBSIZE 256 44 #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } 45 46 /* SCIF */ 47 #define CONFIG_CONS_SCIF4 48 49 #define CONFIG_SYS_MEMTEST_START (KZM_SDRAM_BASE) 50 #define CONFIG_SYS_MEMTEST_END \ 51 (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) 52 #undef CONFIG_SYS_ALT_MEMTEST 53 #undef CONFIG_SYS_MEMTEST_SCRATCH 54 #undef CONFIG_SYS_LOADS_BAUD_CHANGE 55 56 #define CONFIG_SYS_INIT_RAM_ADDR (0xE5600000) /* on MERAM */ 57 #define CONFIG_SYS_INIT_RAM_SIZE (0x10000) 58 #define LOW_LEVEL_MERAM_STACK (CONFIG_SYS_INIT_RAM_ADDR - 4) 59 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 60 CONFIG_SYS_INIT_RAM_SIZE - \ 61 GENERATED_GBL_DATA_SIZE) 62 #define CONFIG_SDRAM_OFFSET_FOR_RT (16 * 1024 * 1024) 63 #define CONFIG_SYS_SDRAM_BASE (KZM_SDRAM_BASE + CONFIG_SDRAM_OFFSET_FOR_RT) 64 #define CONFIG_SYS_SDRAM_SIZE (PHYS_SDRAM_SIZE - CONFIG_SDRAM_OFFSET_FOR_RT) 65 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) 66 67 #define CONFIG_SYS_MONITOR_BASE (KZM_FLASH_BASE) 68 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) 69 #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) 70 71 #define CONFIG_SYS_TEXT_BASE 0x00000000 72 #define CONFIG_STANDALONE_LOAD_ADDR 0x41000000 73 74 /* FLASH */ 75 #define CONFIG_FLASH_CFI_DRIVER 76 #define CONFIG_SYS_FLASH_CFI 77 #undef CONFIG_SYS_FLASH_QUIET_TEST 78 #define CONFIG_SYS_FLASH_EMPTY_INFO 79 #define FLASH_SECTOR_SIZE (256 * 1024) /* 256 KB sectors */ 80 #define CONFIG_ENV_SIZE FLASH_SECTOR_SIZE 81 #define CONFIG_ENV_OFFSET FLASH_SECTOR_SIZE 82 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) 83 84 /* Timeout for Flash erase operations (in ms) */ 85 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) 86 /* Timeout for Flash write operations (in ms) */ 87 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) 88 /* Timeout for Flash set sector lock bit operations (in ms) */ 89 #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) 90 /* Timeout for Flash clear lock bit operations (in ms) */ 91 #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) 92 93 #undef CONFIG_SYS_FLASH_PROTECTION 94 #undef CONFIG_SYS_DIRECT_FLASH_TFTP 95 96 /* GPIO / PFC */ 97 #define CONFIG_SH_GPIO_PFC 98 99 /* Clock */ 100 #define CONFIG_GLOBAL_TIMER 101 #define CONFIG_SYS_CLK_FREQ (48000000) 102 #define CONFIG_SYS_CPU_CLK (1196000000) 103 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ 104 #define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */ 105 106 #define CONFIG_NFS_TIMEOUT 10000UL 107 108 /* I2C */ 109 #define CONFIG_SYS_I2C 110 #define CONFIG_SYS_I2C_SH 111 #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 5 112 #define CONFIG_SYS_I2C_SH_BASE0 0xE6820000 113 #define CONFIG_SYS_I2C_SH_SPEED0 100000 114 #define CONFIG_SYS_I2C_SH_BASE1 0xE6822000 115 #define CONFIG_SYS_I2C_SH_SPEED1 100000 116 #define CONFIG_SYS_I2C_SH_BASE2 0xE6824000 117 #define CONFIG_SYS_I2C_SH_SPEED2 100000 118 #define CONFIG_SYS_I2C_SH_BASE3 0xE6826000 119 #define CONFIG_SYS_I2C_SH_SPEED3 100000 120 #define CONFIG_SYS_I2C_SH_BASE4 0xE6828000 121 #define CONFIG_SYS_I2C_SH_SPEED4 100000 122 #define CONFIG_SH_I2C_8BIT 123 #define CONFIG_SH_I2C_DATA_HIGH 4 124 #define CONFIG_SH_I2C_DATA_LOW 5 125 #define CONFIG_SH_I2C_CLOCK 104000000 /* 104 MHz */ 126 127 #endif /* __KZM9G_H */ 128