xref: /openbmc/u-boot/include/configs/kzm9g.h (revision 7ca6f363)
1 /*
2  * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
3  * Copyright (C) 2012 Renesas Solutions Corp.
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #ifndef __KZM9G_H
9 #define __KZM9G_H
10 
11 #undef DEBUG
12 
13 #define CONFIG_RMOBILE
14 #define CONFIG_SH73A0
15 #define CONFIG_KZM_A9_GT
16 #define CONFIG_RMOBILE_BOARD_STRING	"KMC KZM-A9-GT"
17 #define CONFIG_MACH_TYPE MACH_TYPE_KZM9G
18 
19 #include <asm/arch/rmobile.h>
20 
21 #define CONFIG_ARCH_CPU_INIT
22 #define CONFIG_DISPLAY_CPUINFO
23 #define CONFIG_DISPLAY_BOARDINFO
24 #define CONFIG_BOARD_EARLY_INIT_F
25 #define CONFIG_OF_LIBFDT
26 
27 #include <config_cmd_default.h>
28 #define CONFIG_CMDLINE_TAG
29 #define CONFIG_SETUP_MEMORY_TAGS
30 #define CONFIG_INITRD_TAG
31 #define CONFIG_DOS_PARTITION
32 #define CONFIG_CMD_FAT
33 #define CONFIG_CMD_BOOTZ
34 
35 #define CONFIG_BAUDRATE		115200
36 #define CONFIG_BOOTARGS		"root=/dev/null console=ttySC4,115200"
37 #define CONFIG_BOOTDELAY 3
38 
39 #define CONFIG_VERSION_VARIABLE
40 #undef  CONFIG_SHOW_BOOT_PROGRESS
41 
42 /* MEMORY */
43 #define KZM_SDRAM_BASE	(0x40000000)
44 #define PHYS_SDRAM		KZM_SDRAM_BASE
45 #define PHYS_SDRAM_SIZE		(512 * 1024 * 1024)
46 #define CONFIG_NR_DRAM_BANKS	(1)
47 
48 /* NOR Flash */
49 #define KZM_FLASH_BASE	(0x00000000)
50 #define CONFIG_SYS_FLASH_BASE		(KZM_FLASH_BASE)
51 #define CONFIG_SYS_FLASH_CFI_WIDTH	(FLASH_CFI_16BIT)
52 #define CONFIG_SYS_MAX_FLASH_BANKS	(1)
53 #define CONFIG_SYS_MAX_FLASH_SECT	(512)
54 
55 /* prompt */
56 #define CONFIG_SYS_LONGHELP
57 #define CONFIG_SYS_PROMPT		"KZM-A9-GT# "
58 #define CONFIG_SYS_CBSIZE		256
59 #define CONFIG_SYS_PBSIZE		256
60 #define CONFIG_SYS_MAXARGS		16
61 #define CONFIG_SYS_BARGSIZE		512
62 #define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
63 
64 /* SCIF */
65 #define CONFIG_SCIF_CONSOLE
66 #define CONFIG_CONS_SCIF4
67 #undef  CONFIG_SYS_CONSOLE_INFO_QUIET
68 #undef  CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
69 #undef  CONFIG_SYS_CONSOLE_ENV_OVERWRITE
70 
71 #define CONFIG_SYS_MEMTEST_START	(KZM_SDRAM_BASE)
72 #define CONFIG_SYS_MEMTEST_END \
73 	(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
74 #undef  CONFIG_SYS_ALT_MEMTEST
75 #undef  CONFIG_SYS_MEMTEST_SCRATCH
76 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE
77 
78 #define CONFIG_SYS_INIT_RAM_ADDR	(0xE5600000) /* on MERAM */
79 #define CONFIG_SYS_INIT_RAM_SIZE	(0x10000)
80 #define LOW_LEVEL_MERAM_STACK		(CONFIG_SYS_INIT_RAM_ADDR - 4)
81 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
82 					 CONFIG_SYS_INIT_RAM_SIZE - \
83 					 GENERATED_GBL_DATA_SIZE)
84 #define CONFIG_SDRAM_OFFSET_FOR_RT	(16 * 1024 * 1024)
85 #define CONFIG_SYS_SDRAM_BASE	(KZM_SDRAM_BASE + CONFIG_SDRAM_OFFSET_FOR_RT)
86 #define CONFIG_SYS_SDRAM_SIZE	(PHYS_SDRAM_SIZE - CONFIG_SDRAM_OFFSET_FOR_RT)
87 #define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
88 
89 #define CONFIG_SYS_MONITOR_BASE	(KZM_FLASH_BASE)
90 #define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 128 * 1024)
91 #define CONFIG_SYS_BOOTMAPSZ	(8 * 1024 * 1024)
92 
93 #define CONFIG_SYS_TEXT_BASE		0x00000000
94 #define CONFIG_STANDALONE_LOAD_ADDR	0x41000000
95 
96 /* FLASH */
97 #define CONFIG_FLASH_CFI_DRIVER
98 #define CONFIG_SYS_FLASH_CFI
99 #undef  CONFIG_SYS_FLASH_QUIET_TEST
100 #define CONFIG_SYS_FLASH_EMPTY_INFO
101 #define FLASH_SECTOR_SIZE	(256 * 1024)	/* 256 KB sectors */
102 #define CONFIG_ENV_SIZE		FLASH_SECTOR_SIZE
103 #define CONFIG_ENV_OFFSET	FLASH_SECTOR_SIZE
104 #define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
105 
106 /* Timeout for Flash erase operations (in ms) */
107 #define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)
108 /* Timeout for Flash write operations (in ms) */
109 #define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)
110 /* Timeout for Flash set sector lock bit operations (in ms) */
111 #define CONFIG_SYS_FLASH_LOCK_TOUT		(3 * 1000)
112 /* Timeout for Flash clear lock bit operations (in ms) */
113 #define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)
114 
115 #undef  CONFIG_SYS_FLASH_PROTECTION
116 #undef  CONFIG_SYS_DIRECT_FLASH_TFTP
117 #define CONFIG_ENV_IS_IN_FLASH
118 
119 /* GPIO / PFC */
120 #define CONFIG_SH_GPIO_PFC
121 
122 /* Clock */
123 #define CONFIG_GLOBAL_TIMER
124 #define CONFIG_SYS_CLK_FREQ	(48000000)
125 #define CONFIG_SYS_CPU_CLK	(1196000000)
126 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
127 #define TMU_CLK_DIVIDER		(4)	/* 4 (default), 16, 64, 256 or 1024 */
128 
129 /* Ether */
130 #define CONFIG_NET_MULTI
131 #define CONFIG_CMD_PING
132 #define CONFIG_CMD_DHCP
133 #define CONFIG_SMC911X
134 #define CONFIG_SMC911X_BASE	(0x10000000)
135 #define CONFIG_SMC911X_32_BIT
136 #define CONFIG_NFS_TIMEOUT 10000UL
137 
138 /* I2C */
139 #define CONFIG_CMD_I2C
140 #define CONFIG_SYS_I2C
141 #define CONFIG_SYS_I2C_SH
142 #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 5
143 #define CONFIG_SYS_I2C_SH_BASE0	0xE6820000
144 #define CONFIG_SYS_I2C_SH_SPEED0	100000
145 #define CONFIG_SYS_I2C_SH_BASE1	0xE6822000
146 #define CONFIG_SYS_I2C_SH_SPEED1	100000
147 #define CONFIG_SYS_I2C_SH_BASE2	0xE6824000
148 #define CONFIG_SYS_I2C_SH_SPEED2	100000
149 #define CONFIG_SYS_I2C_SH_BASE3	0xE6826000
150 #define CONFIG_SYS_I2C_SH_SPEED3	100000
151 #define CONFIG_SYS_I2C_SH_BASE4	0xE6828000
152 #define CONFIG_SYS_I2C_SH_SPEED4	100000
153 #define CONFIG_SH_I2C_8BIT
154 #define CONFIG_SH_I2C_DATA_HIGH 4
155 #define CONFIG_SH_I2C_DATA_LOW  5
156 #define CONFIG_SH_I2C_CLOCK     104000000 /* 104 MHz */
157 
158 #endif /* __KZM9G_H */
159