xref: /openbmc/u-boot/include/configs/kzm9g.h (revision 39cb4f3c25a1cafbe867d0951d2d54b475a68990)
1  /* SPDX-License-Identifier: GPL-2.0+ */
2  /*
3   * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
4   * Copyright (C) 2012 Renesas Solutions Corp.
5   */
6  
7  #ifndef __KZM9G_H
8  #define __KZM9G_H
9  
10  #define CONFIG_SH73A0
11  #define CONFIG_MACH_TYPE MACH_TYPE_KZM9G
12  
13  #include <asm/arch/rmobile.h>
14  
15  #define CONFIG_ARCH_CPU_INIT
16  
17  #define CONFIG_CMDLINE_TAG
18  #define CONFIG_SETUP_MEMORY_TAGS
19  #define CONFIG_INITRD_TAG
20  
21  #undef  CONFIG_SHOW_BOOT_PROGRESS
22  
23  /* MEMORY */
24  #define KZM_SDRAM_BASE	(0x40000000)
25  #define PHYS_SDRAM		KZM_SDRAM_BASE
26  #define PHYS_SDRAM_SIZE		(512 * 1024 * 1024)
27  
28  /* NOR Flash */
29  #define KZM_FLASH_BASE	(0x00000000)
30  #define CONFIG_SYS_FLASH_BASE		(KZM_FLASH_BASE)
31  #define CONFIG_SYS_FLASH_CFI_WIDTH	(FLASH_CFI_16BIT)
32  #define CONFIG_SYS_MAX_FLASH_BANKS	(1)
33  #define CONFIG_SYS_MAX_FLASH_SECT	(512)
34  
35  /* prompt */
36  #define CONFIG_SYS_PBSIZE		256
37  #define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
38  
39  /* SCIF */
40  #define CONFIG_CONS_SCIF4
41  
42  #define CONFIG_SYS_MEMTEST_START	(KZM_SDRAM_BASE)
43  #define CONFIG_SYS_MEMTEST_END \
44  	(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
45  #undef  CONFIG_SYS_MEMTEST_SCRATCH
46  #undef  CONFIG_SYS_LOADS_BAUD_CHANGE
47  
48  #define CONFIG_SYS_INIT_RAM_ADDR	(0xE5600000) /* on MERAM */
49  #define CONFIG_SYS_INIT_RAM_SIZE	(0x10000)
50  #define LOW_LEVEL_MERAM_STACK		(CONFIG_SYS_INIT_RAM_ADDR - 4)
51  #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
52  					 CONFIG_SYS_INIT_RAM_SIZE - \
53  					 GENERATED_GBL_DATA_SIZE)
54  #define CONFIG_SDRAM_OFFSET_FOR_RT	(16 * 1024 * 1024)
55  #define CONFIG_SYS_SDRAM_BASE	(KZM_SDRAM_BASE + CONFIG_SDRAM_OFFSET_FOR_RT)
56  #define CONFIG_SYS_SDRAM_SIZE	(PHYS_SDRAM_SIZE - CONFIG_SDRAM_OFFSET_FOR_RT)
57  #define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
58  
59  #define CONFIG_SYS_MONITOR_BASE	(KZM_FLASH_BASE)
60  #define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + 128 * 1024)
61  #define CONFIG_SYS_BOOTMAPSZ	(8 * 1024 * 1024)
62  
63  #define CONFIG_STANDALONE_LOAD_ADDR	0x41000000
64  
65  /* FLASH */
66  #define CONFIG_FLASH_CFI_DRIVER
67  #define CONFIG_SYS_FLASH_CFI
68  #undef  CONFIG_SYS_FLASH_QUIET_TEST
69  #define CONFIG_SYS_FLASH_EMPTY_INFO
70  #define FLASH_SECTOR_SIZE	(256 * 1024)	/* 256 KB sectors */
71  #define CONFIG_ENV_SIZE		FLASH_SECTOR_SIZE
72  #define CONFIG_ENV_OFFSET	FLASH_SECTOR_SIZE
73  #define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
74  
75  /* Timeout for Flash erase operations (in ms) */
76  #define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)
77  /* Timeout for Flash write operations (in ms) */
78  #define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)
79  /* Timeout for Flash set sector lock bit operations (in ms) */
80  #define CONFIG_SYS_FLASH_LOCK_TOUT		(3 * 1000)
81  /* Timeout for Flash clear lock bit operations (in ms) */
82  #define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)
83  
84  #undef  CONFIG_SYS_FLASH_PROTECTION
85  #undef  CONFIG_SYS_DIRECT_FLASH_TFTP
86  
87  /* GPIO / PFC */
88  #define CONFIG_SH_GPIO_PFC
89  
90  /* Clock */
91  #define CONFIG_GLOBAL_TIMER
92  #define CONFIG_SYS_CLK_FREQ	(48000000)
93  #define CONFIG_SYS_CPU_CLK	(1196000000)
94  #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
95  #define TMU_CLK_DIVIDER		(4)	/* 4 (default), 16, 64, 256 or 1024 */
96  
97  #define CONFIG_NFS_TIMEOUT 10000UL
98  
99  /* I2C */
100  #define CONFIG_SYS_I2C
101  #define CONFIG_SYS_I2C_SH
102  #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 5
103  #define CONFIG_SYS_I2C_SH_BASE0	0xE6820000
104  #define CONFIG_SYS_I2C_SH_SPEED0	100000
105  #define CONFIG_SYS_I2C_SH_BASE1	0xE6822000
106  #define CONFIG_SYS_I2C_SH_SPEED1	100000
107  #define CONFIG_SYS_I2C_SH_BASE2	0xE6824000
108  #define CONFIG_SYS_I2C_SH_SPEED2	100000
109  #define CONFIG_SYS_I2C_SH_BASE3	0xE6826000
110  #define CONFIG_SYS_I2C_SH_SPEED3	100000
111  #define CONFIG_SYS_I2C_SH_BASE4	0xE6828000
112  #define CONFIG_SYS_I2C_SH_SPEED4	100000
113  #define CONFIG_SH_I2C_8BIT
114  #define CONFIG_SH_I2C_DATA_HIGH 4
115  #define CONFIG_SH_I2C_DATA_LOW  5
116  #define CONFIG_SH_I2C_CLOCK     104000000 /* 104 MHz */
117  
118  #endif /* __KZM9G_H */
119