11251e490SNobuhiro Iwamatsu /* 21251e490SNobuhiro Iwamatsu * include/configs/koelsch.h 31251e490SNobuhiro Iwamatsu * 41251e490SNobuhiro Iwamatsu * Copyright (C) 2013 Renesas Electronics Corporation 51251e490SNobuhiro Iwamatsu * 61251e490SNobuhiro Iwamatsu * SPDX-License-Identifier: GPL-2.0 71251e490SNobuhiro Iwamatsu */ 81251e490SNobuhiro Iwamatsu 91251e490SNobuhiro Iwamatsu #ifndef __KOELSCH_H 101251e490SNobuhiro Iwamatsu #define __KOELSCH_H 111251e490SNobuhiro Iwamatsu 121251e490SNobuhiro Iwamatsu #undef DEBUG 131251e490SNobuhiro Iwamatsu #define CONFIG_R8A7791 141251e490SNobuhiro Iwamatsu #define CONFIG_RMOBILE_BOARD_STRING "Koelsch" 151251e490SNobuhiro Iwamatsu 165ca6dfe6SNobuhiro Iwamatsu #include "rcar-gen2-common.h" 17b6c96f7fSNobuhiro Iwamatsu 1869191fedSNobuhiro Iwamatsu #if defined(CONFIG_RMOBILE_EXTRAM_BOOT) 1969191fedSNobuhiro Iwamatsu #define CONFIG_SYS_TEXT_BASE 0x70000000 2069191fedSNobuhiro Iwamatsu #else 21c71b4dd2SNobuhiro Iwamatsu #define CONFIG_SYS_TEXT_BASE 0xE6304000 2269191fedSNobuhiro Iwamatsu #endif 2369191fedSNobuhiro Iwamatsu 241251e490SNobuhiro Iwamatsu /* STACK */ 2569191fedSNobuhiro Iwamatsu #if defined(CONFIG_RMOBILE_EXTRAM_BOOT) 2669191fedSNobuhiro Iwamatsu #define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC 2769191fedSNobuhiro Iwamatsu #else 2869191fedSNobuhiro Iwamatsu #define CONFIG_SYS_INIT_SP_ADDR 0xE633fffC 2969191fedSNobuhiro Iwamatsu #endif 3069191fedSNobuhiro Iwamatsu 311251e490SNobuhiro Iwamatsu #define STACK_AREA_SIZE 0xC000 321251e490SNobuhiro Iwamatsu #define LOW_LEVEL_MERAM_STACK \ 331251e490SNobuhiro Iwamatsu (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) 341251e490SNobuhiro Iwamatsu 351251e490SNobuhiro Iwamatsu /* MEMORY */ 365ca6dfe6SNobuhiro Iwamatsu #define RCAR_GEN2_SDRAM_BASE 0x40000000 375ca6dfe6SNobuhiro Iwamatsu #define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024) 385ca6dfe6SNobuhiro Iwamatsu #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) 391251e490SNobuhiro Iwamatsu 401251e490SNobuhiro Iwamatsu /* SCIF */ 411251e490SNobuhiro Iwamatsu #define CONFIG_SCIF_CONSOLE 421251e490SNobuhiro Iwamatsu 431251e490SNobuhiro Iwamatsu /* FLASH */ 44c71b4dd2SNobuhiro Iwamatsu #define CONFIG_SYS_NO_FLASH 45c71b4dd2SNobuhiro Iwamatsu #define CONFIG_SPI 46c71b4dd2SNobuhiro Iwamatsu #define CONFIG_SH_QSPI 47c71b4dd2SNobuhiro Iwamatsu #define CONFIG_SPI_FLASH 48c71b4dd2SNobuhiro Iwamatsu #define CONFIG_SPI_FLASH_BAR 49c71b4dd2SNobuhiro Iwamatsu #define CONFIG_SPI_FLASH_SPANSION 501251e490SNobuhiro Iwamatsu 5190362c0cSNobuhiro Iwamatsu /* SH Ether */ 5290362c0cSNobuhiro Iwamatsu #define CONFIG_NET_MULTI 5390362c0cSNobuhiro Iwamatsu #define CONFIG_SH_ETHER 5490362c0cSNobuhiro Iwamatsu #define CONFIG_SH_ETHER_USE_PORT 0 5590362c0cSNobuhiro Iwamatsu #define CONFIG_SH_ETHER_PHY_ADDR 0x1 5690362c0cSNobuhiro Iwamatsu #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII 5790362c0cSNobuhiro Iwamatsu #define CONFIG_SH_ETHER_CACHE_WRITEBACK 5890362c0cSNobuhiro Iwamatsu #define CONFIG_SH_ETHER_CACHE_INVALIDATE 5990362c0cSNobuhiro Iwamatsu #define CONFIG_PHYLIB 6090362c0cSNobuhiro Iwamatsu #define CONFIG_PHY_MICREL 6190362c0cSNobuhiro Iwamatsu #define CONFIG_BITBANGMII 6290362c0cSNobuhiro Iwamatsu #define CONFIG_BITBANGMII_MULTI 6390362c0cSNobuhiro Iwamatsu #define CONFIG_SH_ETHER_ALIGNE_SIZE 64 6490362c0cSNobuhiro Iwamatsu 651251e490SNobuhiro Iwamatsu /* Board Clock */ 66ae8e1d9dSNobuhiro Iwamatsu #define RMOBILE_XTAL_CLK 20000000u 67ae8e1d9dSNobuhiro Iwamatsu #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK 68ae8e1d9dSNobuhiro Iwamatsu #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) 691251e490SNobuhiro Iwamatsu #define CONFIG_SYS_TMU_CLK_DIV 4 701251e490SNobuhiro Iwamatsu 71bb611cceSNobuhiro Iwamatsu /* i2c */ 72bb611cceSNobuhiro Iwamatsu #define CONFIG_CMD_I2C 73bb611cceSNobuhiro Iwamatsu #define CONFIG_SYS_I2C 74bb611cceSNobuhiro Iwamatsu #define CONFIG_SYS_I2C_SH 75bb611cceSNobuhiro Iwamatsu #define CONFIG_SYS_I2C_SLAVE 0x7F 76bb611cceSNobuhiro Iwamatsu #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3 77bb611cceSNobuhiro Iwamatsu #define CONFIG_SYS_I2C_SH_SPEED0 400000 78bb611cceSNobuhiro Iwamatsu #define CONFIG_SYS_I2C_SH_SPEED1 400000 79bb611cceSNobuhiro Iwamatsu #define CONFIG_SYS_I2C_SH_SPEED2 400000 80bb611cceSNobuhiro Iwamatsu #define CONFIG_SH_I2C_DATA_HIGH 4 81bb611cceSNobuhiro Iwamatsu #define CONFIG_SH_I2C_DATA_LOW 5 82bb611cceSNobuhiro Iwamatsu #define CONFIG_SH_I2C_CLOCK 10000000 83bb611cceSNobuhiro Iwamatsu 84b8f383b8SNobuhiro Iwamatsu #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ 85b8f383b8SNobuhiro Iwamatsu 86aa44ae32SNobuhiro Iwamatsu /* USB */ 87aa44ae32SNobuhiro Iwamatsu #define CONFIG_USB_EHCI 88aa44ae32SNobuhiro Iwamatsu #define CONFIG_USB_EHCI_RMOBILE 895906fadeSNobuhiro Iwamatsu #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 90aa44ae32SNobuhiro Iwamatsu #define CONFIG_USB_STORAGE 91aa44ae32SNobuhiro Iwamatsu 928e2e5886SNobuhiro Iwamatsu /* Module stop status bits */ 938e2e5886SNobuhiro Iwamatsu /* INTC-RT */ 948e2e5886SNobuhiro Iwamatsu #define CONFIG_SMSTP0_ENA 0x00400000 958e2e5886SNobuhiro Iwamatsu /* MSIF*/ 968e2e5886SNobuhiro Iwamatsu #define CONFIG_SMSTP2_ENA 0x00002000 978e2e5886SNobuhiro Iwamatsu /* INTC-SYS, IRQC */ 988e2e5886SNobuhiro Iwamatsu #define CONFIG_SMSTP4_ENA 0x00000180 998e2e5886SNobuhiro Iwamatsu /* SCIF0 */ 1008e2e5886SNobuhiro Iwamatsu #define CONFIG_SMSTP7_ENA 0x00200000 1018e2e5886SNobuhiro Iwamatsu 102*11e32910SNobuhiro Iwamatsu /* SD */ 103*11e32910SNobuhiro Iwamatsu #define CONFIG_MMC 104*11e32910SNobuhiro Iwamatsu #define CONFIG_CMD_MMC 105*11e32910SNobuhiro Iwamatsu #define CONFIG_GENERIC_MMC 106*11e32910SNobuhiro Iwamatsu #define CONFIG_SH_SDHI_FREQ 97500000 107*11e32910SNobuhiro Iwamatsu 1081251e490SNobuhiro Iwamatsu #endif /* __KOELSCH_H */ 109