183b40c31SHolger Brunck /* 283b40c31SHolger Brunck * (C) Copyright 2009 383b40c31SHolger Brunck * Marvell Semiconductor <www.marvell.com> 483b40c31SHolger Brunck * Prafulla Wadaskar <prafulla@marvell.com> 583b40c31SHolger Brunck * 683b40c31SHolger Brunck * (C) Copyright 2009 783b40c31SHolger Brunck * Stefan Roese, DENX Software Engineering, sr@denx.de. 883b40c31SHolger Brunck * 98170aefcSHolger Brunck * (C) Copyright 2011-2012 108170aefcSHolger Brunck * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com 118170aefcSHolger Brunck * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com 1283b40c31SHolger Brunck * 1383b40c31SHolger Brunck * See file CREDITS for list of people who contributed to this 1483b40c31SHolger Brunck * project. 1583b40c31SHolger Brunck * 1683b40c31SHolger Brunck * This program is free software; you can redistribute it and/or 1783b40c31SHolger Brunck * modify it under the terms of the GNU General Public License as 1883b40c31SHolger Brunck * published by the Free Software Foundation; either version 2 of 1983b40c31SHolger Brunck * the License, or (at your option) any later version. 2083b40c31SHolger Brunck * 2183b40c31SHolger Brunck * This program is distributed in the hope that it will be useful, 2283b40c31SHolger Brunck * but WITHOUT ANY WARRANTY; without even the implied warranty of 2383b40c31SHolger Brunck * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 2483b40c31SHolger Brunck * GNU General Public License for more details. 2583b40c31SHolger Brunck * 2683b40c31SHolger Brunck * You should have received a copy of the GNU General Public License 2783b40c31SHolger Brunck * along with this program; if not, write to the Free Software 2883b40c31SHolger Brunck * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 2983b40c31SHolger Brunck * MA 02110-1301 USA 3083b40c31SHolger Brunck */ 3183b40c31SHolger Brunck 3283b40c31SHolger Brunck /* 3383b40c31SHolger Brunck * for linking errors see 3483b40c31SHolger Brunck * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html 3583b40c31SHolger Brunck */ 3683b40c31SHolger Brunck 3783b40c31SHolger Brunck #ifndef _CONFIG_KM_KIRKWOOD_H 3883b40c31SHolger Brunck #define _CONFIG_KM_KIRKWOOD_H 3983b40c31SHolger Brunck 40e29c6d04SHolger Brunck #if defined(CONFIG_KM_KIRKWOOD) 4183b40c31SHolger Brunck #define CONFIG_IDENT_STRING "\nKeymile Kirkwood" 42d9354530SHolger Brunck #define CONFIG_HOSTNAME km_kirkwood 4383b40c31SHolger Brunck #undef CONFIG_KIRKWOOD_PCIE_INIT 448170aefcSHolger Brunck #define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ 45e29c6d04SHolger Brunck #elif defined(CONFIG_KM_KIRKWOOD_PCI) 4683b40c31SHolger Brunck #define CONFIG_IDENT_STRING "\nKeymile Kirkwood PCI" 47d9354530SHolger Brunck #define CONFIG_HOSTNAME km_kirkwood_pci 488170aefcSHolger Brunck #define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ 498170aefcSHolger Brunck /* KM_NUSA */ 508170aefcSHolger Brunck #elif defined(CONFIG_KM_NUSA) 518170aefcSHolger Brunck #define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/ 528170aefcSHolger Brunck #define CONFIG_IDENT_STRING "\nKeymile NUSA" 53d9354530SHolger Brunck #define CONFIG_HOSTNAME kmnusa 548170aefcSHolger Brunck #undef CONFIG_SYS_KWD_CONFIG 558170aefcSHolger Brunck #define CONFIG_SYS_KWD_CONFIG \ 568170aefcSHolger Brunck $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg 578170aefcSHolger Brunck #define CONFIG_KM_ENV_IS_IN_SPI_NOR 588170aefcSHolger Brunck #define CONFIG_KM_FPGA_CONFIG 598170aefcSHolger Brunck #define CONFIG_KM_PIGGY4_88E6352 608170aefcSHolger Brunck 61*f945439aSHolger Brunck /* KM_MGCOGE3UN */ 62*f945439aSHolger Brunck #elif defined(CONFIG_KM_MGCOGE3UN) 63*f945439aSHolger Brunck #define CONFIG_IDENT_STRING "\nKeymile COGE3UN" 64*f945439aSHolger Brunck #define CONFIG_HOSTNAME mgcoge3un 65*f945439aSHolger Brunck #define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/ 66*f945439aSHolger Brunck #undef CONFIG_SYS_KWD_CONFIG 67*f945439aSHolger Brunck #define CONFIG_SYS_KWD_CONFIG \ 68*f945439aSHolger Brunck $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-memphis.cfg 69*f945439aSHolger Brunck #define CONFIG_KM_BOARD_EXTRA_ENV "waitforne=true\0" 70*f945439aSHolger Brunck #define CONFIG_PIGGY_MAC_ADRESS_OFFSET 3 71*f945439aSHolger Brunck #define CONFIG_KM_DISABLE_PCIE 72*f945439aSHolger Brunck #define CONFIG_KM_PIGGY4_88E6061 73*f945439aSHolger Brunck 74*f945439aSHolger Brunck /* KMCOGE5UN */ 75d9354530SHolger Brunck #elif defined(CONFIG_KM_COGE5UN) 76d9354530SHolger Brunck #define CONFIG_IDENT_STRING "\nKeymile COGE5UN" 77d9354530SHolger Brunck #define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/ 78d9354530SHolger Brunck #undef CONFIG_SYS_KWD_CONFIG 79d9354530SHolger Brunck #define CONFIG_SYS_KWD_CONFIG \ 80d9354530SHolger Brunck $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_256M8_1.cfg 81d9354530SHolger Brunck #define CONFIG_KM_ENV_IS_IN_SPI_NOR 82d9354530SHolger Brunck #define CONFIG_PIGGY_MAC_ADRESS_OFFSET 3 83d9354530SHolger Brunck #define CONFIG_HOSTNAME kmcoge5un 84d9354530SHolger Brunck #define CONFIG_KM_DISABLE_PCIE 85d9354530SHolger Brunck #define CONFIG_KM_PIGGY4_88E6352 868170aefcSHolger Brunck #else 878170aefcSHolger Brunck #error ("Board unsupported") 8883b40c31SHolger Brunck #endif 8983b40c31SHolger Brunck 908170aefcSHolger Brunck /* include common defines/options for all arm based Keymile boards */ 918170aefcSHolger Brunck #include "km/km_arm.h" 928170aefcSHolger Brunck 938170aefcSHolger Brunck #ifndef CONFIG_KM_ENV_IS_IN_SPI_NOR 9483b40c31SHolger Brunck #define KM_ENV_BUS "pca9544a:70:d" /* I2C2 (Mux-Port 5)*/ 958170aefcSHolger Brunck #endif 968170aefcSHolger Brunck 978170aefcSHolger Brunck #if defined(CONFIG_KM_PIGGY4_88E6352) 988170aefcSHolger Brunck /* 998170aefcSHolger Brunck * Some keymile boards like mgcoge5un & nusa1 have their PIGGY4 connected via 1008170aefcSHolger Brunck * an Marvell 88E6352 simple switch. 1018170aefcSHolger Brunck * In this case we have to change the default settings for the etherent mac. 1028170aefcSHolger Brunck * There is NO ethernet phy. The ARM and Switch are conencted directly over 1038170aefcSHolger Brunck * RGMII in MAC-MAC mode 1048170aefcSHolger Brunck * In this case 1GBit full duplex and autoneg off 1058170aefcSHolger Brunck */ 1068170aefcSHolger Brunck #define PORT_SERIAL_CONTROL_VALUE ( \ 1078170aefcSHolger Brunck MVGBE_FORCE_LINK_PASS | \ 1088170aefcSHolger Brunck MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \ 1098170aefcSHolger Brunck MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \ 1108170aefcSHolger Brunck MVGBE_ADV_NO_FLOW_CTRL | \ 1118170aefcSHolger Brunck MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ 1128170aefcSHolger Brunck MVGBE_FORCE_BP_MODE_NO_JAM | \ 1138170aefcSHolger Brunck (1 << 9) /* Reserved bit has to be 1 */ | \ 1148170aefcSHolger Brunck MVGBE_DO_NOT_FORCE_LINK_FAIL | \ 1158170aefcSHolger Brunck MVGBE_DIS_AUTO_NEG_SPEED_GMII | \ 1168170aefcSHolger Brunck MVGBE_DTE_ADV_0 | \ 1178170aefcSHolger Brunck MVGBE_MIIPHY_MAC_MODE | \ 1188170aefcSHolger Brunck MVGBE_AUTO_NEG_NO_CHANGE | \ 1198170aefcSHolger Brunck MVGBE_MAX_RX_PACKET_1552BYTE | \ 1208170aefcSHolger Brunck MVGBE_CLR_EXT_LOOPBACK | \ 1218170aefcSHolger Brunck MVGBE_SET_FULL_DUPLEX_MODE | \ 1228170aefcSHolger Brunck MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\ 1238170aefcSHolger Brunck MVGBE_SET_GMII_SPEED_TO_1000 |\ 1248170aefcSHolger Brunck MVGBE_SET_MII_SPEED_TO_100) 1258170aefcSHolger Brunck 1268170aefcSHolger Brunck #endif 12783b40c31SHolger Brunck 128*f945439aSHolger Brunck #ifdef CONFIG_KM_PIGGY4_88E6061 129*f945439aSHolger Brunck /* 130*f945439aSHolger Brunck * Some keymile boards like mgcoge3un have their PIGGY4 connected via 131*f945439aSHolger Brunck * an Marvell 88E6061 simple switch. 132*f945439aSHolger Brunck * In this case we have to change the default settings for the 133*f945439aSHolger Brunck * ethernet phy connected to the kirkwood. 134*f945439aSHolger Brunck * In this case 100MB full duplex and autoneg off 135*f945439aSHolger Brunck */ 136*f945439aSHolger Brunck #define PORT_SERIAL_CONTROL_VALUE ( \ 137*f945439aSHolger Brunck MVGBE_FORCE_LINK_PASS | \ 138*f945439aSHolger Brunck MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \ 139*f945439aSHolger Brunck MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \ 140*f945439aSHolger Brunck MVGBE_ADV_NO_FLOW_CTRL | \ 141*f945439aSHolger Brunck MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ 142*f945439aSHolger Brunck MVGBE_FORCE_BP_MODE_NO_JAM | \ 143*f945439aSHolger Brunck (1 << 9) /* Reserved bit has to be 1 */ | \ 144*f945439aSHolger Brunck MVGBE_DO_NOT_FORCE_LINK_FAIL | \ 145*f945439aSHolger Brunck MVGBE_DIS_AUTO_NEG_SPEED_GMII | \ 146*f945439aSHolger Brunck MVGBE_DTE_ADV_0 | \ 147*f945439aSHolger Brunck MVGBE_MIIPHY_MAC_MODE | \ 148*f945439aSHolger Brunck MVGBE_AUTO_NEG_NO_CHANGE | \ 149*f945439aSHolger Brunck MVGBE_MAX_RX_PACKET_1552BYTE | \ 150*f945439aSHolger Brunck MVGBE_CLR_EXT_LOOPBACK | \ 151*f945439aSHolger Brunck MVGBE_SET_FULL_DUPLEX_MODE | \ 152*f945439aSHolger Brunck MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\ 153*f945439aSHolger Brunck MVGBE_SET_GMII_SPEED_TO_10_100 |\ 154*f945439aSHolger Brunck MVGBE_SET_MII_SPEED_TO_100) 155*f945439aSHolger Brunck #endif 156*f945439aSHolger Brunck 157f0d64257SHolger Brunck /* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */ 158f0d64257SHolger Brunck #define KM_XLX_PROGRAM_B_PIN 39 159f0d64257SHolger Brunck 160*f945439aSHolger Brunck #ifdef CONFIG_KM_DISABLE_PCI 161*f945439aSHolger Brunck #undef CONFIG_KIRKWOOD_PCIE_INIT 162*f945439aSHolger Brunck #endif 16383b40c31SHolger Brunck #endif /* _CONFIG_KM_KIRKWOOD */ 164